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LM4051-N
SNOS491D – FEBRUARY 2000 – REVISED SEPTEMBER 2018
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1.2 VREF Simplified Schematic Adjustable Reference Simplified Schematic
VDD VDD
RS VOUT = 1.225 V RS VOUT = ADJ
Anode R1
LM4051-1.2
LM4051-ADJ
Cathode
R2
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM4051-N
SNOS491D – FEBRUARY 2000 – REVISED SEPTEMBER 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 10
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 10
3 Description ............................................................. 1 9 Application and Implementation ........................ 11
4 Revision History..................................................... 2 9.1 Application Information............................................ 11
9.2 Typical Applications ................................................ 12
5 Pin Configuration and Functions ......................... 3
9.3 System Examples ................................................... 14
6 Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3 10 Power Supply Recommendations ..................... 18
6.2 ESD Ratings.............................................................. 3 11 Layout................................................................... 18
6.3 Recommended Operating Conditions....................... 4 11.1 Layout Guidelines ................................................. 18
6.4 Thermal Information .................................................. 4 11.2 Layout Example .................................................... 18
6.5 LM4051-1.2 Electrical Characteristics ...................... 4 12 Device and Documentation Support ................. 19
6.6 LM4051-ADJ Electrical Characteristics..................... 5 12.1 Receiving Notification of Documentation Updates 19
6.7 Typical Characteristics .............................................. 7 12.2 Community Resources.......................................... 19
7 Parameter Measurement Information .................. 9 12.3 Trademarks ........................................................... 19
12.4 Electrostatic Discharge Caution ............................ 19
8 Detailed Description ............................................ 10
12.5 Glossary ................................................................ 19
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10 13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Device Information table, Device Comparison table, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1
Pin Functions
PIN
I/O DESCRIPTION
NAME 1.2 V ADJ
Anode 2 3 O Shunt Current/Voltage input
Cathode 1 2 I/O Common pin, normally connected to ground
NC 3 - - Must float or connect to anode
FB - 1 I Threshold relative to cathode
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Reverse current 20 mA
Forward current 10 mA
Maximum output voltage (LM4051-ADJ) 15 V
Power dissipation (TA = 25°C) (2) M3 package 280 mW
Vapor phase (60 seconds) 215
Lead temperature M3 packages °C
Infrared (15 seconds) 220
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax= (TJmax −TA )/ θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For the LM4051-N,
TJmax = 125°̊ C, and the typical thermal resistance (θJA), when board mounted, is 280°C/W for the SOT-23 package.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
(3) The machine model is a 200-pF capacitor discharged directly into each pin.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) This overtemperature limit for Reverse Breakdown Voltage Tolerance is defined as the room temperature Reverse Breakdown Voltage
Tolerance ± [(∆VR/∆T)(max∆T)(VR)]. Where, ∆VR/∆T is the VR temperature coefficient, max∆T is the maximum difference in
temperature from the reference point of 25°̊ C to TMAX or TMIN, and VR is the reverse breakdown voltage. The total overtemperature
tolerance for the different grades in the industrial temperature range where max∆T=65 ̊C is shown below:
(a) A-grade: ± 0.425% = ± 0.1% ± 50 ppm/°̊ C x 65°̊ C
(b) B-grade: ± 0.525% = ± 0.2% ± 50 ppm/°̊ C x 65°̊ C
(c) C-grade: ± 0.825% = ± 0.5% ± 50 ppm/°̊ C x 65°̊ C
Therefore, as an example, the A-grade LM4051-1.2 has an over-temperature Reverse Breakdown Voltage tolerance of ± 1.2V x 0.425%
= ± 5.2 mV.
(2) Limits are 100% production tested at 25 ̊C. Limits over temperature are guaranteed through correlation using Statistical Quality Control
(SQC) methods. The limits are used to calculate National’s AOQL.
4 Submit Documentation Feedback Copyright © 2000–2018, Texas Instruments Incorporated
(1) This overtemperature limit for Reverse Breakdown Voltage Tolerance is defined as the room temperature Reverse Breakdown Voltage
Tolerance ± [(∆VR/∆T)(max∆T)(VR)]. Where, ∆VR/∆T is the VR temperature coefficient, max∆T is the maximum difference in temperature
from the reference point of 25°̊ C to TMAX or TMIN, and VR is the reverse breakdown voltage. The total overtemperature tolerance for the
different grades in the industrial temperature range where max∆T = 65 ̊C is shown below:
(a) A-grade: ± 0.425% = ± 0.1% ± 50 ppm/°̊ C × 65°̊ C
(b) B-grade: ± 0.525% = ± 0.2% ± 50 ppm/°̊ C × 65°̊ C
(c) C-grade: ± 0.825% = ± 0.5% ± 50 ppm/°̊ C × 65°̊ C
Therefore, as an example, the A-grade LM4051-1.2 has an overtemperature Reverse Breakdown Voltage tolerance of ± 1.2 V × 0.425%
= ± 5.2 mV.
(2) Reference voltage and temperature coefficient will change with output voltage. See Typical Characteristics curves.
(3) Limits are 100% production tested at 25 ̊C. Limits over temperature are ensured through correlation using Statistical Quality Control
(SQC) methods. The limits are used to calculate National’s AOQL.
Copyright © 2000–2018, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LM4051-N
LM4051-N
SNOS491D – FEBRUARY 2000 – REVISED SEPTEMBER 2018 www.ti.com
(4) Limits are 100% production tested at 25 ̊C. Limits over temperature are guaranteed through correlation using Statistical Quality Control
(SQC) methods. The limits are used to calculate National’s AOQL.
(5) When VOUT ≤ 1.6 V, the LM4051-ADJ in the SOT-23 package must operate at reduced IR. This is caused by the series resistance of the
die attach between the die (–) output and the package (–) output pin. See the Output Saturation curve in the Typical Characteristics
section.
(6) Long-term stability is VR at 25°̊ C measured during 1000 hrs.
(7) Thermal hysteresis is defined as the difference in voltage measured at +25 ̊C after cycling to temperature –40 ̊C and the 25 ̊C
measurement after cycling to temperature +125 ̊C.
Figure 7. Reference Voltage vs Temperature and Output Figure 8. Feedback Current vs Output Voltage and
Voltage Temperature
Figure 9. Output Saturation (SOT-23 Only) Figure 10. Output Impedance vs Frequency
8 Detailed Description
8.1 Overview
The LM4051-N is a precision voltage reference available in SOT-23 surface mount package. The LM4051-N is
available in a 1.225 V fixed-option as well as an adjustable voltage option. The LM4051-N comes in three
different tolerance grades (A, B, and C). The best grade devices (A) have an initial accuracy of 0.1%, while the
B-grade have 0.2% and the C-grade 0.5%, all with a temperature coefficient of 50 ppm/˚C guaranteed from
−40˚C to 125˚C.
*LM4051-ADJ only
**LM4051-1.2 only
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
where
• VO is the output voltage (2)
VS - VR
RS =
IL + IQ + IF
(3)
The actual value of the internal VREF is a function of VO. The corrected VREF is determined by Equation 4:
VR EF = VO (D VR EF / D VO ) + VY
where
• VY = 1.22 V (4)
§ R1 ·
VO = ¨1+ ¸ × VREF I REF × R1
© R2¹ (8)
Figure 21. Bounded Amplifier Reduces Saturation-induced Delays and Can Prevent Succeeding Stage
Damage. Nominal Clamping Voltage is ±VO (LM4051-N's Reverse Breakdown Voltage) +2 Diode VF .
*D1 can be any LED, VF = 1.5V to 2.2V at 3 mA. D1 may act as an indicator. D1 will be on if ITHRESHOLD falls below
the threshold current, except with I = O.
11 Layout
RS
CIN COUT
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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