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403GCX-3BC50C2 Datasheet

  • 403GCX-3BC50C2

  • 32-Bit Microprocessor

  • 619.14KB

  • 56页

  • ETC

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IBM
PowerPC 403GCX
Table 18. 403GCX Synchronous Output Timings
25 MHz
Symbol
33 MHz
T
OHMin
Min
40 MHz
T
OHMin
Min
Parameter
Output float time
T
OF1
T
OF4
T
OF5
T
OF6
T
OF9
T
OF10
T
OF13
T
OF14
T
OF16
T
OF17
T
OF20
T
OHMin
Min
T
OVMa
x
T
OVMa
x
T
OVMa
Units
x
T
OF
Max
Max
Max
A6:31
CAS0:3
CS0:7
D0:31
DRAMOE
DRAMWE
OE
RAS0:3
Reset
R/W
WBE0:3[BE0:3]
2
3
3
3
3
3
3
3
2
3
3
8
10
10
10
9
9
9
10
9
9
9
2
3
3
3
3
3
3
3
2
3
3
8
10
10
10
9
9
9
10
9
9
9
2
3
3
3
3
3
3
3
2
3
3
8
10
10
10
9
9
9
10
9
9
9
ns
Notes:
1. For all output timing, T
OH
and T
OV
are relative to the rising edge of SysClk.
2. For detailed EDO DRAM timing waveforms, refer to "EDO DRAM 2-1-1-1 Burst Read Followed by Single Transfer
Read," on page 45 and "EDO DRAM 3-1-1-1 Burst Read Followed by Single Transfer Read," on page 47.
3. The Address bus, RAS, CAS and DRAMOE output timings (with respect to the falling edge of the internal duty
cycle corrected SysClk) vary with the 403GCX operating frequency. Use the following equations to determine the
worst-case output delay and hold times for these signals: T
OVf
Max = Tc/2 + T
OVr
Max; T
OHf
Min = Tc/2 + T
OHr
Min,
where T
OVr
Max and T
OHr
Min correspond to the specifications for the speed grade of the part. Valid for Tc greater
than 25 ns and less than 41.7 ns.
4. In early RAS mode, the RAS output delay varies with the 403GCX operating frequency. Use the following equation
to determine the worst-case output delay for this signal: T
OV15
Max = Tc/4 + T
OH15
Min, where T
OH15
Min corre-
sponds to the specification for the speed grade of the part. T
OH
Min remains unchanged. Valid for Tc greater than
25 ns and less than 41.7 ns.
5. Parity timings are for DMA buffered mode. For normal memory accesses, use the data bus timings for parity.
6. Output times are measured with a standard 50 pF capacitive load, unless otherwise noted. Output hold times are
measured as T
OVmin
at 3.47V and Tj=0掳C.
7. All output hold and float times are guaranteed by design and not tested.
8. Noted output valid times guaranteed by design and not tested.
9. 403GCX-3JC80A and 403GCX-3BC80A with application relief applied meet all 40 MHz synchronous output tim-
ings.
Table 19. 403GCX DRAM Interface Timing Relationships
Symbol
Parameter
Row Address Setup Time to RAS:
BRn[ERM] = 0
BRn[ERM] = 1
Row Address Hold Time:
BRn[ERM] = 0
BRn[ERM] = 1
Column Address Setup Time to CAS
Column Address Hold Time
25 MHz
Min
33 MHz
Min
40 MHz
Min
Units
T
ASR
0.5T
C
-4.0
0.25T
C
-2.5
0.5T
C
-1.5
0.67T
C
-0.5
0.5T
C
-4.0
0.5T
C
-2.0
0.5T
C
-4.0
0.25T
C
-2.5
0.5T
C
-1.5
0.67T
C
-0.5
0.5T
C
-4.0
0.5T
C
-2.0
0.5T
C
-4.0
0.25T
C
-2.5
0.5T
C
-1.5
0.67T
C
-0.5
0.5T
C
-4.0
0.5T
C
-2.0
ns
T
RAH
T
ASC
T
CAH
ns
ns
ns
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