SN65LVDS306: behaviour of CPOL

user5796274

Part Number: SN65LVDS306

The Datasheet specifies on Page 6 the following for the input pin CPOL:

0 - rising edge clocking

1 - falling edge clocking

Whereas Figure 4 on Page 8 shows, that the data is clocked out with the falling edge if CPOL = 0. At least the Comment in brackets implies it (CPOL=0)

What is the correct behaviour of CPOL?

Thanks for your help

over 5 years ago

0 Ikechukwu Anyiam over 5 years ago

TI__Mastermind 35130 points

Hello,

That figure shows data being clocked in on the rising edge. Please see the ideal strobe position in Figure 7 on page 15.

Regards,
I.K.

0 user5796274 over 5 years ago in reply to Ikechukwu Anyiam

Prodigy 40 points

so that means that the Transmitter, in this case the SN65LVDS306, will use the falling edge to update the R,G,B and frame sync signals, and CPOL=0 enables the falling edge to transmit the data ? (and therefor the Receiver will clock in the data with the rising edge...as you mentioned in your answer)

0 Ikechukwu Anyiam over 5 years ago in reply to user5796274

TI__Mastermind 35130 points

I'm not sure what you mean. The SN65LVDS306 is a receiver, and when CPOL=0 it will clock data in on the rising edge of PCLK. You can take a look at Figure 8 for another visual representation.

Regards,
I.K.

0 user5796274 over 5 years ago in reply to Ikechukwu Anyiam

Prodigy 40 points

CPOL defines the Output clock polarity according to the datasheet.
I'm trying to find out if the R,G,B, HS etc. signals, which are output to the attached Display Controller change with the falling or rising edge of PCLK.
I think the only data input to this IC are the D+, D- respectively the CLK+, CLK- SubLVDS Pins

Thanks for your help

Regards
M.B.

0 Ikechukwu Anyiam over 5 years ago in reply to user5796274

TI__Mastermind 35130 points

My mistake, you're correct about the inputs and PCLK. I believe CPOL selects rising/falling edge polarity for receivers that only accept one. For example, if a receiver can only strobe data in on the rising edge of PCLK then you would set CPOL=0 on the LVDS306.

Regards,
I.K.

0 user5796274 over 5 years ago in reply to Ikechukwu Anyiam

Prodigy 40 points

Thanks for your reply.

Is it really CPOL=0 -> rising edge? That's what I'm confused about.

The Table on Page 6 says so but Figure 4 on Page 8 shows the opposite. There the data is clocked out with neg edge and the comment says (CPOL=0)

(Figure 8 and Figure 13 also show changing data with neg edge PCLK)

Thanks for your help

0 Ikechukwu Anyiam over 5 years ago in reply to user5796274

TI__Mastermind 35130 points

Hi,

Yeah, it's CPOL=0 -> rising edge, meaning whatever is connected to the 306 must strobe in data on the rising edge of PCLK. I believe that is what the figures are illustrating.

Regards,
I.K.

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SN65LVDS306: behaviour of CPOL