A method and apparatus for maximizing the performance of DMA transfers over a PCI.TM. bus are provided which includes a Per-Channel Retry count, Double Buffer Management, Wait Enable functionality, Back Up register functionality, Gather/Scatter mapping, a method for minimization of PIO writes, Read Semaphore...http://www.google.com.hk/patents/US5968153?utm_source=gb-gplus-share專利 US5968153 - Mechanism for high bandwidth DMA transfers in a PCI environment
