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FIG. 7 | TO | T1 | T2 | T3 | T4 | T5 | T6 | U | T8 | T9 | T10 |
1st 2nd 3rd 4th
| TO | T1 | T2 | T3 | T4 | T5 | T6 | U | T8 | T9 | T10 | T11 |
1st 2nd 3rd 4th 5th 6th 7th 8th
INTERLEAVED AND SEQUENTIAL COUNTER
BACKGROUND OF THE INVENTION 5
The present invention generally relates to systems and methods for counting. Particularly, the invention relates to a simplified counter capable of supporting several different count schemes.
To achieve higher speed systems, manufacturers are producing more specialized electronic component parts. For example, central processing units (CPUs) are being designed for use in conjunction with either linear-burst or interleavedburst memory systems. In a linear-burst system, memory 15 addresses are accessed in a sequential order. In contrast, an interleaved-burst memory system addresses memory in a non-sequential, or interleaved fashion.
Memory manufacturers, on the other hand, have continued to develop memory systems which function only in 20 conjunction with interleaved-burst CPUs or which function only in conjunction with linear-burst CPUs. This approach is undesirable for several reasons. First, it requires that memory system manufacturers design, produce, fabricate, and assemble different designs and layouts for two relatively 25 similar memory systems. It also forces manufacturers to maintain different inventories and supply channels for those components, thereby increasing the overall cost and overhead associated with each component.
One solution to this problem would be to integrate cir- 30 cuitry for interleaved counts and circuitry for sequential counts onto each memory component. This solution, however, is also undesirable as the additional unused circuitry would occupy valuable substrate and lead space which could otherwise be used to increase memory capacity or capability. 35
There is, therefore, a need for a single counter system which accommodates both interleaved and sequential count schemes.
The present invention offers a single counter system which may be used in devices utilizing either interleaved or sequential counts, thereby eliminating the need to design, 4J produce, inventory, and select between counters which generate only a single count scheme.
A counter system according to the present invention has a first counter seeded by several input signals and a second counter seeded by at least a first output from the first counter. 50 A selection signal is input to the second counter to select the use of either an interleaved count or a sequential count. In one specific embodiment, the first counter is seeded, or provided with a starting count, using signals indicating a burst length. This allows use of the counter system in a 55 synchronous dynamic random access memory (SDRAM). The first counter performs a sequential binary count of every system clock cycle. The second counter, also a binary counter, may be seeded from outputs from the first counter to generate an interleaved count. The second counter may go also be seeded from a clock signal to function as a sequential counter.
The result is an adaptable counter system which is capable of functioning at high speed, making the device well suited for applications such as memories which may be used with 65 either interleaved or sequential count CPUs. The device may be provided with a reset function which resets the count.
Further, inputs may be provided which indicate a specific length of count to be performed.
Although the present invention is discussed in terms of a specific embodiment for use in conjunction with a memory system, those skilled in the art will realize that the counter system may be utilized in any application requiring an ability to count in either interleaved or sequential count modes.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a counter system according to one specific embodiment of the invention;
FIG. 2 is a more detailed diagram of a burst length counter used in the counter system of FIG. 1;
FIG. 3 is a circuit diagram of one binary counter used in the burst length counter of FIG. 2;
FIG. 4 is a circuit diagram of a y-address counter of the counter system of FIG. 1;
FIG. 5 is a circuit diagram of the y-address counter of FIG. 4;
FIG. 6 is a plot of a timing diagram of the burst length counter of FIG. 2;
FIG. 7 is a plot of a timing diagram of the y-address counter of FIG. 4 for a sequential count with a burst length of four; and
FIG. 8 is a plot of a timing diagram of the y-address counter of FIG. 4 for an interleaved count with a burst length of eight.
DESCRIPTION OF THE PREFERRED
Features of the present invention will now be described by first referring to FIG. 1 where a counter system 10 of the invention is shown. The counter system 10 includes a burst length counter 1 which operates in conjunction with a y-address counter 2. The two counters together operate to create several output signals, including y-addresses 7 which are output to, e.g., y-address predecoders in a SDRAM system. The y-addresses 7 output from the system 10 may be output in either interleaved or sequential fashion. The system 10 also outputs a ybst_end signal which is used to signal the completion of a burst operation. The counter system 10 outputs these signals based upon several inputs.
The burst length counter 1 includes, in one specific embodiment, four inputs designed to establish a specific length of burst to be counted. These four inputs, BL1, BL2, BL4, and BL8 may, e.g., be provided to the counter system 10 from a mode register or the like. As will be described, the four inputs function to establish the maximum count of a three-bit binary counter. Specifically, if BL1 is set to "1" and all other inputs are a logic "0", the burst length will be one. If BL2 is a logic "1" and all other inputs are "0", the burst length will be two. A logic "1" on the BL4 input indicates a four count burst length, and a "1" on the BL8 line establishes a count length of eight. Those skilled in the art will recognize that other signal sequences may be employed to indicate a desired count length. Further, the desired count length may be preset or hardwired as a specific, constant length. A RESET signal or other means may be utilized to reset the burst length counter 1.
Each of the counters 1, 2 are controlled by a count increment signal cntinc__tO, which is synchronized to the system clock. The y-address counter 2 is controlled by a delayed version of the cntinc___tO signal (cntinc_t2). The count increment signal cntinc_tO is delayed, in one specific 5 embodiment, through the use of two inverters 5, 6. The amount of delay is chosen such that the count increment signal cntinc_t2 is delayed approximately the same amount of time it takes to output signals bcntO and bcntl from burst length counter 1. Thus, in the embodiment depicted in FIG. 10 1, counter 2 is seeded, or started, by two signals output from burst length counter 1. Accordingly, counter system 10 utilizes one binary counter which is seeded from an outside source (such as a mode register) and a second binary counter which is seeded by output signals from the first counter. 15
Y-address counter 2 has several other inputs. The seq„ int# signal determines the type of count scheme to be employed. For example, in one specific embodiment, a seq_int# asserted high indicates a sequential (binary) count scheme while asserting the signal low may indicate the use 20 of an interleaved count scheme. The seq_int# signal, like the burst lengths input to the burst length counter 1, may be input from a mode register or the like.
A LATCH signal is also input to the y-address counter 2. The LATCH signal, as will be discussed, is used to latch a 25 starting address into latches contained in the y-address counter 2. In the specific embodiment depicted, the y-address of a memory location at which a burst access is to start is input to the y-address counter 2. As a highly simplified example, if the burst is to start from address number 0000, 30 a 0000 will be input to the y-address counter 2 through y-address lines. Those skilled in the art will recognize that any size of address may be accommodated by the present invention. Further, those skilled in the art will also recognize that data other than memory addresses may be used to start 35 the counter of the present invention.
When the LATCH signal is asserted (at the beginning of a burst cycle), the address indicated on address line ya[0:n] is latched into y-address counter 2. As will be discussed 4Q further herein, the starting y-address propagates to the output lines. Multiplexors 3,4 may be used to select between address lines. That is, for the starting address of a burst, multiplexor 4 may be selected to directly propagate the starting addresses to address line 7. For subsequent counts of 45 the burst, multiplexor 3 may be used to pass the addresses generated by the y-address counter 2.
The operation and configuration of the burst length counter 2 will now be described in more detail by first referring to FIG. 2. In one specific embodiment supporting 50 a burst length of up to eight, the burst length counter 2 includes three binary counters 11-13 coupled in sequence. Counters 11,12 and 13 are resettable binary counters which change output signals (A1-A3) with every falling edge of the count increment control signal cntinc„t0. Each counter 55 accepts three inputs: the cntinc_t0 signal; a signal indicating states of previous counter stages facAl-3; and a RESET signal. The facAl-3 signals reflect the state of output of each of the previous counters 11-13.
Because counter 11 is the first of the three counters (i.e., 60 there is no previous counter), the signal facAl is tied to VDD. The signal facA2 input to counter 12 is tied to the output Al of the previous counter, counter 11. FacA3, input to counter 13, is the result of a logical AND of the outputs of counter 11 (facAl) and counter 12 (facA2). The result is a three bit 65 binary counter which counts up from 000 to 111. The coupling of counters 11-13 in this manner reduces the time
delay required for all counter stages to switch states. Specifically, each of the counters 11-13 change their state with the same amount of delay (measured, in this specific embodiment, from a falling edge of the count increment signal cntinc_t0) when their input facAl-3 is a logic "1". This results in an ability to perform simple binary counts at very high clock frequencies, e.g., on the order of 60 MHz or greater.
The composition of each of the counters 11-13 is similar and may be understood by referring to FIG. 3. Each increments, or outputs a logic "1" on the falling edge of the cntinc„t0 signal when the facAn input signal is also a logic "1". Each counter is also provided with circuitry allowing a reset of the counter's output An to a logic "0". In each of the counters 11-13, a RESET signal line is coupled to a PMOS transistor 63. When the RESET signal is asserted, the PMOS transistor 63 is turned on allowing node 53 to charge to a logic "1". The RESET signal is only asserted when the cntinc_t0 signal is a logic "0". At that time the transmission gate formed by MOS transistors 70,71 is in an on condition. The transmission gate allows the signal at node 53 to be inverted through inverters 68, 74 and 76 thereby resetting the counter to produce a stable logic "0" at the output An. This reset function may be timed to occur in conjunction with a burst command to ensure that all counter stages are properly reset.
The general function and timing of the operation of the burst length counter 1 is shown in the timing diagram of FIG. 6. In the example of FIG. 6, a burst length of four is used. That is, a mode register or the like has set input line BL4 high, while BL1, BL2, and BL8 are each set to a logic "0". When BL4 is a logic "1", transistor 36 of FIG. 2 is turned on, while transistors 32,34 and 44 are each turned off. When the burst length counter 1 reaches the fourth clock cycle, bcntO (which is output from counter 11) goes high as does bcntl (output from counter 12). The bcntl and bcntO signals are ANDed together in AND gate 37 to produce a logic "0", which is then inverted by inverter 38 to create a logic "1", thereby turning transistor 35 on. This allows node 21 to discharge to ground. The next cntinc_t0 finally turns transistor 42 on, placing node 22 at a logic "0". This signal is inverted by inverter 45 to produce a ybst_end signal to signal the end of the four count burst length.
In addition to producing a signal indicating the end of a burst cycle, the burst length counter 1 also produces two signals which are input to the y-address counter 2. Specifically, intermediate count bits bcntO and bcntl are used to seed the y-address counter 2. Referring now to FIG. 4 it is seen that the y-address counter 2 consists of, in one specific embodiment, at least three counter stages 77, 78, 79 and an address latch 80. The three least significant bits of the address lines are input, respectively, as yaO, yal, and ya2 into counters 77, 78, and 79. The remaining address bits ya[3:n] are stored in latch 80. The use of three counters 77-79 allows burst counts of up to eight (i.e., 000 through 111). Upon reading this disclosure, those skilled in the art will recognize that the present invention may be used to accommodate greater burst lengths by providing a greater number of counters in both the burst length counter 1 and in the y-address counter 2.
Each counter 77-79 has the general configuration shown in FIG. 5. The counters include a set means 131, an interleaved-type count control means 132, a sequential type count control means 133, and a basic counter means 134. The basic counter means 134 is similar to the counters contained in the burst length counter 1. The set means 131 is used to set a beginning y-address to node 97 through