1
MEMORY CELL COMPRISING A
SEMICONDUCTOR JUNCTION DIODE
CRYSTALLIZED ADJACENT TO A SILICIDE
RELATED APPLICATIONS 5
This application is a continuation-in-part of Petti et al., U.S. patent application Ser. No. 10/728,230, "Semiconductor Device Including Junction Diode Contacting ContactAnfifuse Unit Comprising Silicide," filed Dec. 3, 2002 now 10 U.S. Pat. No. 6,946,719, hereinafter the '230 application, assigned to the assignee of the present invention and hereby incorporated by reference.
This application is related to Herner et al., U.S. application Ser. No. 10/954,577, "Junction Diode Comprising Vary- 15 ing Semiconductor Compositions," hereinafter the '577 application; to Herner et al., U.S. application Ser. No. 10/955,549, "Nonvolatile Memory Cell Without a Dielectric Antifuse Having High- and Low-Impedance States," hereinafter the '549 application; and to Petti et al., U.S. appli- 20 cation Ser. No. 10/955,387, "Fuse Memory Cell Comprising a Diode, the Diode Serving as the Fuse Element," all assigned to the assignee of the present invention, all filed on even date herewith and all hereby incorporated by reference in their entirety. 25
BACKGROUND OF THE INVENTION
The invention relates to a memory cell comprising a low-impedance semiconductor junction diode formed in 30 proximity to a silicide and an antifuse.
Herner et al., U.S. patent application Ser. No. 10/326,470, "An Improved Method for Making High Density Nonvolatile Memory," filed Dec. 19, 2002 and hereinafter the '470 application, which is hereby incorporated by reference, 35 employs a vertically oriented semiconductor junction diode interposed between conductors, the diode separated from at least one of the conductors by a dielectric rupture antifuse, or having a dielectric rupture antifuse interposed between diode portions. 40
In some circumstances, the programming voltage required to program this memory cell may be greater than desired. There is a need, therefore, to form a diode-antifuse memory cell having a reduced programming voltage.
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SUMMARY OF THE PREFERRED
EMBODIMENTS
The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on 50 those claims. In general, the invention is directed to a memory cell comprising a low-resistance semiconductor junction diode crystallized in contact with a silicide, the semiconductor junction diode in series with an antifuse.
A first aspect of the invention provides for a method for 55 forming a memory cell, the method comprising: forming first semiconductor diode portions; forming a first layer of a silicide-forming metal; forming a first oxide, nitride, or oxynitride layer disposed between the first silicide-forming metal layer and one of the first semiconductor diode portions 60 and in contact with both; and annealing the first semiconductor diode portions, first silicide-forming metal layer, and first oxide, nitride, or oxynitride layer to substantially entirely reduce the first oxide, nitride, or oxynitride layer between the silicide and the first semiconductor diode por- 65 tions and to form a first silicide layer by siliciding a fraction of one or more of the first diode portions.
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Another aspect of the invention provides for a method for forming a first plurality of memory cells, the method comprising: forming a plurality of substantially parallel first conductors extending in a first direction at a first height above a substrate; forming a plurality of first semiconductor pillars at a second height above the substrate, wherein the second height is different from the first height; forming a plurality of first silicide layers in contact with each first semiconductor pillar; forming a plurality of first dielectric rupture antifuses disposed between the first silicide layers and the first conductors and in contact with both.
A preferred embodiment of the invention provides for a method for forming a first memory level of memory cells in a memory array, the method comprising: forming a plurality of first conductors at a first height above a substrate in a first pattern and etch step; forming a plurality of semiconductor pillars above the first conductors in a second pattern and etch step; crystallizing the plurality of first semiconductor pillars, wherein each of the first semiconductor pillars is in contact with a silicide at the time it is crystallized; forming a plurality of second conductors above the first semiconductor pillars in a third pattern and etch step; and forming a plurality of dielectric rupture antifuses between the first and second conductors, each antifuse in series with a first semiconductor pillar of the plurality of first semiconductor pillars, and each antifuse in contact with one of the conductors, wherein the first, second, and third pattern and etch steps are all separate.
An aspect of the invention provides for a method for forming a monolithic three dimensional memory array, the method comprising: forming a plurality of substantially parallel first conductors extending in a first direction at a first height above a substrate, the first conductors not comprising silicide; forming a plurality of substantially parallel second conductors extending in a second direction at a second height above the substrate, the second conductors not comprising silicide, wherein the second height is different from the first height; forming a plurality of first junction diodes disposed between the first conductors and the second conductors, wherein each of the junction diodes contacts one of a plurality of silicide layers, wherein the first conductors, first junction diodes, and second conductors make up a first memory level; and monolithically forming a second memory level above the first memory level.
Another aspect of the invention provides for a memory level of nonvolatile programmable memory cells comprising: a plurality of substantially parallel first conductors formed at a first height above a substrate; a plurality of first pillars formed at a second height above the first height, each pillar comprising a silicide layer; a plurality of substantially parallel second conductors formed at a third height above the second height; and a plurality of dielectric rupture antifuses, each between one of the plurality of first pillars and one of the plurality of first or second conductors.
A preferred embodiment of the invention provides for a monolithic three dimensional memory array comprising: a first memory level, the first memory level comprising: a plurality of substantially parallel, substantially coplanar bottom conductors; a plurality of substantially parallel, substantially coplanar top conductors above the bottom conductors; a plurality of pillars, each pillar disposed between one of the bottom conductors and one of the top conductors, and each pillar comprising a silicide layer; and a plurality of dielectric regions, each between one of the pillars and one of the conductors; and a second memory level monolithically formed above the first memory level.
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Each of the aspects and embodiments of the invention described herein can be used alone or in combination with one another.
The preferred aspects and embodiments will now be described with reference to the attached drawings. 5
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective view of a memory cell comprising a vertically oriented junction diode and a dielectric rupture 10 antifuse disposed between top and bottom conductors.
FIG. 2 is a perspective view of a memory cell comprising a vertically oriented junction diode having no dielectric rupture antifuse disposed between top and bottom conductors.
FIG. 3 is a perspective view of a memory cell formed according to the present invention comprising a vertically oriented junction diode adjacent to a silicide layer and in series with an antifuse. 20
FIGS. 4a-4d are cross-sectional views illustrating fabrication of a plurality of memory cells formed according to the present invention.
FIGS. 5a-5d are cross-sectional views showing preferred junction diodes for use in a memory cell. 25
DETAILED DESCRIPTION OF THE
PREFERRED EMBODIMENTS
A semiconductor junction diode, for example a p-n diode 30 or a p-i-n diode, has been paired with a dielectric rupture antifuse to form a memory cell, for example in the monolithic three dimensional memory array described in the '470 application.
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The term junction diode is used herein to refer to a semiconductor device with the property of conducting current more easily in one direction than the other, having two terminal electrodes, and made of semiconducting material which is p-type at one electrode and n-type at the other. 4Q Examples include p-n diodes and n-p diodes, which have p-type semiconductor material and n-type semiconductor material in contact, and p-i-n and n-i-p diodes, in which intrinsic (undoped) semiconductor material is interposed between p-type semiconductor material and n-type semicon- 45 ductor material.
A preferred memory cell of the '470 application includes a vertically oriented junction diode disposed between conductors, the cell further having a dielectric rupture antifuse interposed between the junction diode and one of the con- 50 ductors. A memory cell 2 according to the '470 application is shown in FIG. 1. A first conductor 20 preferably comprises titanium nitride layer 4 and tungsten layer 6. Junction diode 30 is formed on optional titanium nitride barrier layer 8 and comprises heavily doped semiconductor layer 10 of a first 55 conductivity type, layer 12 which is undoped semiconductor material or lightly doped semiconductor material of a second conductivity type, and heavily doped semiconductor layer 14 of the second conductivity type. A thin silicon dioxide antifuse layer 16 is formed on top of the junction diode 30. 60 Second conductor 40 preferably comprises titanium nitride layer 18 and tungsten layer 22. Silicon dioxide layer 16 operates as a dielectric rupture antifuse.
The memory cell 2 is unprogrammed as formed. As formed, the cell is in an initial high-impedance state with 65 little or no current flow, and after application of a programming voltage, the cell is in a low-impedance state with
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significantly increased current flow. To program the memory cell, a programming voltage is applied between conductors 20 and 40.
As taught in the application Ser. No. 10/955,549, the memory cell of embodiments of the '470 application has been modified by omitting the dielectric rupture antifuse (silicon dioxide layer 16 in FIG. 1.) It has been found that the resulting memory cell exhibits similar behavior: As formed, the cell is in an initial high-impedance state with little or no current flow, and after application of a programming voltage, the cell is in a low-impedance state with significantly increased current flow. Such a memory cell 3, having no dielectric rupture antifuse, is shown in FIG. 2.
While not wishing to be bound by any particular theory, it may be that application of a programming voltage to the memory cell of the application Ser. No. 10/955,549, changes the characteristics of junction diode 30, which is typically formed of polycrystalline silicon (polysilicon), changing the resistance of junction diode 30. One possibility is that the polysilicon of junction diode 30 is formed in a highresistance state, and a low-resistance filament is formed through the pillar upon application of a programming voltage.
It has been found that a programming voltage of six to eight volts is required to convert the junction diode 30 of memory cell 3 from a high-impedance to a low-impedance state. For many applications, it is desirable to reduce the voltage required to program a cell.
In embodiments of the present invention, in a memory cell similar to the ones shown in FIGS. 1 and 2, the semiconductor junction diode 30 is formed in a low-impedance state. This low-impedance state is apparently induced if amorphous silicon junction diode 30 is crystallized while in contact with a metal silicide. The metal silicide may provide a template for crystal growth of the silicon, decreasing the density of silicon defects. It is particularly advantageous to form the silicide by 1) depositing silicon, 2) forming an oxide, nitride, or oxynitride on the silicon, 3) forming a silicide-forming metal on the oxide, nitride, or oxynitride, then 4) annealing to reduce the oxide, nitride, or oxynitride and, in the same anneal step, form the silicide by reaction of the silicide-forming metal with the silicon. A dielectric rupture antifuse is then formed in series with the lowimpedance junction diode, forming a memory cell.
In general, then, such a cell can be formed by forming first semiconductor diode portions; forming a first layer of a silicide-forming metal; forming a first oxide, nitride, or oxynitride layer disposed between the first silicide-forming metal layer and one of the first semiconductor diode portions and in contact with both; and annealing the first semiconductor diode portions, first silicide-forming metal layer, and first oxide, nitride, or oxynitride layer to substantially entirely reduce the first oxide, nitride, or oxynitride layer between the silicide and the first semiconductor diode portions and to form a first silicide layer by siliciding a fraction of one or more of the first diode portions.
A memory cell 5 formed according to the present invention is shown in FIG. 3. Most of the layers are the same as in the cell of FIG. 1, including first conductor 20 of titanium nitride layer 4 and tungsten layer 6. Junction diode 30 is formed on optional titanium nitride barrier layer 8 and comprises heavily doped semiconductor layer 10 of a first conductivity type, layer 12 which is undoped semiconductor material or lightly doped semiconductor material of a second conductivity type, and heavily doped semiconductor layer 14 of the second conductivity type. A silicide layer 15 is formed at the top of the junction diode 30, and a dielectric
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antifuse layer 16 is formed on top of silicide layer 15. Second conductor 40 preferably comprises titanium nitride layer 18 and tungsten layer 22.
To compare the memory cells of FIG. 1 and FIG. 3, each shown before programming: Each includes a dielectric rup- 5 ture antifuse 16 and a junction diode 30. The junction diode 30 of FIG. 1, however, is formed in a high-impedance state, while the junction diode 30 of FIG. 3 is formed in a low-impedance state. Both memory cells are programmed by applying a programming voltage across the cell. In both 10 cells, in order to program the cell, the dielectric rupture antifuse 16 must be ruptured. To program the cell of FIG. 1 it is also necessary to convert junction diode 30 from a high-impedance to a low-impedance state; the cell of FIG. 3 is already in a low-impedance state. 15
A detailed example will be provided of fabrication of an array of memory cells formed according to aspects of the present invention. For completeness, many details of materials, process conditions, and steps will be provided. It will be understood, however, that many details can be changed, 20 omitted or supplemented while the results fall within the scope of the invention.
Fabrication
The '470 application described fabrication of a monolithic 25 three dimensional memory array comprising memory cells like those of FIG. 1. The '230 application described fabrication of a monolithic three dimensional memory array comprising a related memory cell. The methods and procedures taught in those applications, with modifications 30 described in this discussion, can provide guidance in formation of monolithic three dimensional memory arrays comprising diode-antifuse memory cells. For clarity, not all of the details of the '470 and '230 applications will be included, but it will be understood that no teaching of these 35 applications is intended to be excluded.
Fabrication of a single memory level is described in detail. Additional memory levels can be stacked, each monolithically formed above the one below it.
Turning to FIG. 4a, formation of the memory begins with 40 a substrate 100. This substrate 100 can be any semiconducting substrate as known in the art, such as monocrystalline silicon, IV—IV compounds like silicon-germanium or silicon-germanium-carbon, III-V compounds, II-VII compounds, epitaxial layers over such substrates, or any other 45 semiconducting material. The substrate may include integrated circuits fabricated therein.
An insulating layer 102 is formed over substrate 100. The insulating layer 102 can be silicon oxide, silicon nitride, high-dielectric film, Si—C—O—H film, or any other suit- 50 able insulating material.
The first conductors 200 are formed over the substrate and insulator. An adhesion layer 104 may be included between the insulating layer 102 and the conducting layer 106 to help the conducting layer 106 adhere. Preferred materials for the 55 adhesion layer 104 are tantalum nitride, tungsten nitride, titanium tungsten, sputtered tungsten, titanium nitride, or combinations of these materials. If the overlying conducting layer is tungsten, titanium nitride is preferred as an adhesion layer. 60
If adhesion layer 104 is included, it can be deposited by any process known in the art. Where adhesion layer 104 is titanium nitride, it can be formed by depositing a titanium nitride material, or by depositing titanium, which is then subject to a nitridation process. The titanium nitride can be 65 deposited by any chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process such as sputtering,
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or an atomic layer deposition (ALD) process. In one embodiment, the titanium nitride material is deposited by a sputtering process.
The thickness of adhesion layer 104 can range from about 20 to about 500 angstroms. In one embodiment, the thickness of adhesion layer 104 is about 200 angstroms. Note that in this discussion, "thickness" will denote vertical thickness, measured in a direction perpendicular to substrate 100.
The next layer to be deposited is conducting layer 106. Conducting layer 106 can comprise any conducting material known in the art, including tantalum, titanium, tungsten, copper, cobalt, or alloys thereof. Titanium nitride may be used. Where conducting layer 106 is tungsten, it can be deposited by any CVD process or a PVD process. In one embodiment, the tungsten is deposited by a CVD process. The thickness of conducting layer 106 can depend, in part, on the desired sheet resistance and therefore can be any thickness that provides the desired sheet resistance. In one embodiment, the thickness of conducting layer 106 can range from about 200 to about 2000 angstroms. In another embodiment, the thickness of conducting layer 106 is about 1500 angstroms.
If tungsten is used for conducting layer 106, it is preferred to use a barrier layer between the tungsten and the semiconductor material that will be part of the semiconductor pillars that will eventually overlie the conductors. Such a barrier layer serves to prevent reaction between tungsten and silicon. The barrier layer may either be patterned with the conductor rails or with the semiconductor pillars.
If a barrier layer is to be used, and is to be formed as the top layer of the conductor rails, the barrier layer should be deposited after the conducting layer 106. (The barrier layer is not shown in FIG. 4a.) Any material serving this function can be used in the barrier layer, including tungsten nitride, tantalum nitride, titanium nitride, or combinations of these materials. In a preferred embodiment, titanium nitride is used as the barrier layer. Where the barrier layer is titanium nitride, it can be deposited in the same manner as the adhesion layer described earlier.
Once all the layers that will form the conductor rails have been deposited, the layers will be patterned and etched using any suitable masking and etching process to form substantially parallel, substantially coplanar conductors 200, shown in FIG. 4a in cross-section. In one embodiment, photoresist is deposited, patterned by photolithography and the layers etched, and then the photoresist removed, using standard process techniques such as "ashing" in an oxygen-containing plasma, and strip of remaining polymers formed during etch in a liquid solvent such as EKC.
The width of conductor rails 200 after etch can range from about 300 to about 2500 angstroms. (In this discussion "width" will refer to the width of a line or feature measured in the plane substantially parallel to substrate 100.) The width of the gaps between conductor rails 200 preferably is substantially the same as the width of conductor rails 200 themselves, though it may be greater or less. In one embodiment, the width of conductor rails is about 1500 angstroms, as is the width of the intervening gaps.
Next a dielectric material 108 is deposited over and between conductor rails 200. Dielectric material 108 can be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon oxide is used as dielectric material 108. The silicon oxide can be deposited using any known process, such as CVD, or, for example, high density plasma CVD (HDPCVD).
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