DELEGATING NETWORK PROCESSOR OPERATIONS TO STAR TOPOLOGY SERIAL BUS INTERFACES

US 20080184008A1

(io) Pub. No.: US 2008/0184008 Al (43) Pub. Date: Jul. 31, 2008

(54) DELEGATING NETWORK PROCESSOR

OPERATIONS TO STAR TOPOLOGY SERIAL
BUS INTERFACES

(76) Inventors: Julianne Jiang Zhu, Los Gatos,
CA (US); David T. Hass, Santa
Clara, CA (US)

Correspondence Address:
ZILKA-KOTAB, PC- RMI
P.O. BOX 721120
SAN JOSE, CA 95172-1120

(21) Appl.No.: 12/019,576

(22) Filed: Jan. 24, 2008

Related U.S. Application Data

(63) Continuation of application No. 11/831,887, filed on Jul. 31, 2007, which is a continuation-in-part of application No. 10/930,937, filed on Aug. 31, 2004, which is a continuation-in-part of application No. 10/898, 008, filed on Jul. 23, 2004, now Pat. No. 7,334,086, which is a continuation-in-part of application No. 10/682,579, filed on Oct. 8, 2003, now abandoned.

(60) Provisional application No. 60/490,236, filed on Jul. 25, 2003, provisional application No. 60/416,838, filed on Oct. 8, 2002.

Publication Classification

(51) Int. CI.

G06F15/76 (2006.01)
G06F 9/02 (2006.01)

(52) U.S. CI 712/29; 712/E09.002

(57) ABSTRACT

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging net work is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.