Procedure for optimizing mergeability and datapath widths of data flow graphs

(54) PROCEDURE FOR OPTIMIZING

MERGEABILITY AND DATAPATH WIDTHS
OF DATA FLOW GRAPHS

(75) Inventors: Sanjeev Saluja, Jalvayu Vihar (IN);

Anmol Mathur, San Jose, CA (US)

(73) Assignee: Cadence Design Systems, Inc., San

Jose, CA (US)

( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 23 days.

(21) Appl. No.: 10/172,941

(22) Filed: Jun. 17, 2002

(65) Prior Publication Data

US 2003/0061574 Al Mar. 27, 2003

Related U.S. Application Data

(60) Provisional application No. 60/298,536, filed on Jun. 15, 2001.

(51) Int. CI.7 G06F 17/50

(52) U.S. CI 716/2; 716/5; 716/18

(58) Field of Search 716/1, 2, 3, 4,

716/5, 6, 7, 18, 15, 8, 10, 9, 11, 17; 717/156,

158, 160, 155

5,870,308 A * 2/1999 Dangelo et al 716/18

6,026,228 A 2/2000 Imai et al.

6,192,504 Bl 2/2001 Pfluger et al.

6,216,252 Bl * 4/2001 Dangelo et al 716/1

6,237,021 Bl 5/2001 Drammond

6,421,809 Bl * 7/2002 Wuytack et al 716/2

6,463,560 Bl * 10/2002 Bhawmik et al 714/733

6,505,328 Bl 1/2003 Van Ginneken et al.

OTHER PUBLICATIONS

Kim et al (IEEE Transactions on computer-aided design ol integrated circuits and system, vol. 17, No. 10 Oct. 1998).*

Kim et al (IEEE Transactions on computer-aided design ol integrated circuits and system, vol. 19, No. 5, May 2000).*

Taewhan et al (IEEE Transactions on computer-sided design ol integrated circuits and system, vol. 17, No. 10 Oct. 1998).

Taewhan et al (IEEE Transactions on computer-sided design ol integrated circuits and system, vol. 19, No. 5 May 2000).

Huffman, D. A., "A Method lor the Construction ol Minimum-Redundancy Codes" Proceedings of the IRE, (1952) 40(9):1098-1101.

Kim, Y. and T. Kim, "Accurate Exploration ol Timing and Area Trade-offs in Arithmetic Optimization using Carry-Save-Adders" IEEE (Feb., 2001) pp. 622-627.

(List continued on next page.)

Primary Examiner—-Vuthe Siek
Assistant Examiner—Binh C. Tat

(74) Attorney, Agent, or Firm—Bingham McCutchen LLP

OTHER PUBLICATIONS

Kim, Y. and T. Kim, "An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization using Carry-Save Adder Cells" Proc. 43rd IEEE Midwest Symp. on Circuits and Systems, Lansing, Michigan, (Aug., 2000) pp. 338-341.

Kim, T. et al., "Circuit Optimization Using Carry-Save-Adder Cells" IEEE (Oct., 1998) 17(10):974-984. Kim, T. et al., "Arithmetic Optimization using Carry-Save-Adders" Proceedings of the 35th Design Automation Conference (1998) pp. 433-438. Klauser, A. and D. Grunwald, "Instruction Fetch Mechanisms for Multipath Execution Processors" IEEE (1999) pp. 38^17.

Koch, A., "Structured Design Implementation—A Strategy for Implementing Regular Datapaths on FPGAs" FPGA '96 Monterey, CA (1996) pp. 489-513.

Omondi, A.R., "Computer Arithmetic Systems: Algorithms, Architectures and Implementations" (1998) AppendicesA& B, Prentice-Hall International Series in Computer Science, Hertfordshire, United Kingdom.

Rudolph, M. et al., "Test Scheduling and Controller Synthesis in the CADDY-System" IEEE (1991) pp. 278-282.

Rundensteiner, E. A. and D.D. Gajski, "Functional Synthesis
Using Area and Delay Optimization" 29th ACM/IEEE
Design Automation Conference (1992) pp. 291-296.
Um, J. et al., "Optimal Allocation of Carry-Save-Adders in
Arithmetic Optimization" Proceedings of International
Conference on Computer Aided Design (1999) pp. 410-413.
Um, J. et al. "A Fine-Grained Arithmetic Optimization
Technique for High-Performance/Low Power Data Path
Synthesis" Proceedings of the 37th Design Automation Con-
ference (2000) pp. 98-103.

Wallace, C. S., "A Suggestion for a Fast Multiplier" IEEE
Transactions on Electronic Computers (Feb., 1964)
EC-13:14-17.

Weste, N. and K. Eshraghian, "Principles of CMOS VLSI Design—A System Perspective" (1985) pp. 366, 389-391, 401-402, Addition Wesley Publishing Company, Reading, MA.

Willems, M. et al., "System Level Fixed-Point Design Based on an Interpolative Approach" Proceedings of the 34th Design Automation Conference (1997) pp. 293-298. International Search Report, PCT/US02/19138, Cadence Design Systems, Inc., Oct. 6, 2003.

* cited by examiner