Ferroelectric memory device

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(12) United States Patent

Hoya et al.

(io) Patent No.: (45) Date of Patent:

US 7,092,274 B2 Aug. 15, 2006

(54) FERROELECTRIC MEMORY DEVICE

(75) Inventors: Katsuhiko Hoya, Yokohama (JP);

Daisaburo Takashima, Yokohama (JP);
Nobert Rehm, Yokohama (JP)

(73) Assignees: Kabushiki Kaisha Toshiba, Tokyo
(JP); Infineon Technologies, AG,

Munich (DE)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 10/963,589

(22) Filed: Oct. 14, 2004

(65) Prior Publication Data

US 2005/0047188 Al Mar. 3, 2005

Related U.S. Application Data

(62) Division of application No. 10/461,367, filed on Jun. 16, 2003, now Pat. No. 6,822,891.

(51) Int. CI.

G11C11/22 (2006.01)

(52) U.S. CI 365/145; 365/149; 365/202;

365/210; 365/206

(58) Field of Classification Search 365/145,

365/149, 202, 210, 206 See application file for complete search history.

(56) References Cited

U.S. PATENT DOCUMENTS

5,943,256 A 8/1999 Shimitzu et al.

6,046,926 A * 4/2000 Tanaka et al 365/145

6,151,242 A * 11/2000 Takashima 365/145

6,198,652 Bl 3/2001 Kawakubo et al.

6,236,605 Bl * 5/2001 Mori et al 365/205

6,473,331 Bl * 10/2002 Takashima 365/145

6,493,251 Bl * 12/2002 Hoya et al 365/145

6,574,133 Bl * 6/2003 Takashima 365/145

6,822,891 Bl* 11/2004 Hoya et al 365/145

6,826,072 Bl* 11/2004 Takashima 365/145

2003/0058701 Al 3/2003 Takashima

FOREIGN PATENT DOCUMENTS

EP 0 905 785 A2 3/1999

JP 10-200061 7/1998

JP 0200329707 A * 10/2003

* cited by examiner

OTHER PUBLICATIONS

D. Takashima, et al., Symposium on VLSI Circuits Digest of Technical Papers, pp. 83-84, "High-Density Chain Ferroelectric Random-Access Memory (CFRAM)", Jun. 1997.

Primary Examiner—Viet Q. Nguyen

(74) Attorney, Agent, or Firm—Obion, Spivak, McClelland,

Maier & Neustadt, PC.

A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and having the same structure as the memory cell.

8 Claims, 9 Drawing Sheets