Package having very thin semiconductor chip, multichip module assembled by ...

(54) PACKAGE HAVING VERY THIN

SEMICONDUCTOR CHIP, MULTICHIP
MODULE ASSEMBLED BY THE PACKAGE,
AND METHOD FOR MANUFACTURING
THE SAME

(75) Inventor: Junichi Asada, Kawasaki (JP)

(73) Assignee: Kabushiki Kaisha Toshiba, Kawasaki (JP)

( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 09/828,131

(22) Filed: Apr. 9, 2001

Related U.S. Application Data

(62) Division of application No. 09/484,032, filed on Jan. 18, 2000, now Pat. No. 6,239,496.

(30) Foreign Application Priority Data

Jan. 18, 1998 (JP) 11-9763

(51) Int. CI.7 H01L 21/44; H01L 21/48;

H01L 21/50

(52) U.S. CI 438/108; 438/106; 438/459

(58) Field of Search 438/106, 108,

438/459

(56) References Cited

U.S. PATENT DOCUMENTS

5,334,857 A 8/1994 Mennitt et al 257/48

5,376,825 A 12/1994 Tukamoto et al 257/685

5,468,997 A 11/1995 Imai et al 257/734

5,506,383 A * 4/1996 Chen

5,521,122 A * 5/1996 Kuramochi

5,571,754 A * 11/1996 Bertin et al.

5,656,552 A * 8/1997 Hudak et al.

5,657,537 A * 8/1997 Saia et al.

5,677,569 A 10/1997 Choi et al 257/686

5,726,493 A 3/1998 Yamashita et al 257/698

5,798,564 A 8/1998 Eng et al 257/686

5,994,166 A * 11/1999 Akram et al.

6,013,948 A 1/2000 Akram et al 257/698

6,020,629 A 2/2000 Farnworth et al 257/686

6,028,365 A 2/2000 Akram et al 257/778

6,037,665 A 3/2000 Miyazaki 257/773

6.051.886 A 4/2000 Fogal et al 257/777

6.051.887 A 4/2000 Hubbard 257/777

6,087,717 A 7/2000 Ano et al 257/684

6,242,279 Bl * 6/2001 Ho et al.

FOREIGN PATENT DOCUMENTS

JP 8-236694 9/1996

JP 11-145381 5/1999

* cited by examiner

Primary Examiner—David L. Talbott
Assistant Examiner—David Zarneke

(74) Attorney, Agent, or Firm—Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.

(57) ABSTRACT

A semiconductor package ol this invention has an insulating substrates, wiring layers disposed on the surface ol the insulating substrate, a semiconductor chip disposed in a device hole provided in the insulating substrate, inner-jointconductors for connecting at least part ol the bonding pads on the surface ol the semiconductor chip to the corresponding inner-joint-conductors and connection lands connected to the wiring layers. The device hole is provided so that it goes through the center ol the insulating substrate. The semiconductor chip is thinner than the insulating substrate. Then, this semiconductor chip is disposed in the device hole such that a bottom thereol is flush with a bottom plane ol the insulating substrate. Further, this invention provides a MCM in which plural pieces ol the thin semiconductor packages are laminated. In the MCM, the semiconductor packages are laminated such that top and bottom laces ol the thin silicon chip are inverted. Predetermined connection lands are electrically connected to each other through a connecting conductor. This MCM has a high mechanical strength in its stacked structure and there is a low possibility that crack may occur in the package due to stress in the bending direction.

6 Claims, 15 Drawing Sheets