Data processing device and method

. Re isters Re isters Re Isters Registers Input Dafi) (Registers /(“1:l25\ /%l30\ /§|]25\ /130\ ‘I02 ' ' 7' ' . . . . . . ' ' A . . ' ' A 1:13,g1ey;\8:8 8:1 81% 8:8 888 881 I 888 888 ; V V V V V I V V V V E -, I """"" "1 Internal General I ' E lnstructifJ(r)12 ‘I I Purpose Register I I REQISIIBFS I---851-—l ________________ __ ____] _________________ __ ____§ 120\ I Rd2 Rd3 p ‘ v 17 (140 v v r°éiEi$ Rm’ 6616 M M 116/, R_ Fu0 Ful Flow 4;6 45 IC Loop . Fu2 Fu3 \ Counter _ Rlb 135 140 118/ F‘/O F‘/1 \ v v v Data\v V v I-UT Jump Back 1:] Register 10 Fvz FV3 DF Pail/hi DF V V V V V V V V V U00 U01 U02 U03 BR BR B O B 1 BR BR B 2 B 3 we V61 V62 v63 ROD Rm R02 R°3 0O 1O B380 B381 20 so B332 B383 L W " Y J \/ \/ \ / \ / 106 104 U° and "° OW‘ Data 112 611866: 611816: 61866: 61?‘ 1 - u u u Regmers egsters Fu and Fv Data Evepnt Data Evepnt |nFt_\?ergg|t§r|g9 Registers Registers Registers Registers

FIG. '1

Ri0 Ri1' Ri2 RI3 Input Data RIO-3
Registers
/ 100
Rc0 R00 '/ R‘?
RIO Ri1 R12 Rl3 '
RdO'
V I Ii I
< RC1 R01 R90 V V RdO R00-3
I '
Instruction Rm RC1 Rm _\110
Registers " I " I RC2 V Rdzl Internal
General
R02 Rc2 RC3 Rd3I Purpose
Rd2' Rd3' Registers
ii ii 1/ ii V “A
RC3 RC3 -R00 R01 R02 R03 \
\104
K I Output
ii 11 V Data
R00 R01 R02 Just one PAE (not drawn to scale) Registers
PAE Frequency 200MHz
Bus Frequency 5OMHz
XPP V2 Function .
PAE Frequency 50MHz I/9 A"°Cat'°n.
Bus Frequency SOMHZ Register Allocation
Step 1 Step 2 Step 33 Step 56

FIG. 2

Ri0 Ri1 Ri2 Ri3 Input Data Rio-3
Registers
( 100
/ RcO
Rc0 Rc0 ' 3
Rdo RiO Ri1 Ri2 Ri3 '
v i v i I
RC1 RC1 RC0 V v Rdo R008
108%
instruction Rdo RC1 _ Rdl ‘\ 110
Registers v vi n i RC2 Rdz Internal
RC2 RC2 general
RC3 Rd3 “Pose
Rd0 Rd1 Registers
v v v v " “J
RC3 RC3 R00 R01 R02 R03 \_104
K i l Output
D t
V R1730 R01 R02 Just one PAE (ndt drawn to scale) Rggaisters
PAE Frequency 200MHz
Bus Frequency 50MHz
XPP V2 Function -
PAE Frequency 50|VlHZ R '/§3tA'r'l'Bma"'°2'.
Bus Frequency 50MHz eg S e oca ‘on
Step 1 Step 2 Step 3a Step 3Tb

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