CPU system performance is improved by reducing the time required to complete a DRAM access by microprocessors such as the 386DX, 386SX and 80286 by incorporating a programmable DRAM controller therewith which permits consecutive DRAM accesses to average N+0.5 processor wait states. The half wait state...http://www.google.com.hk/patents/US5636367?utm_source=gb-gplus-share專利 US5636367 - N+0.5 wait state programmable DRAM controller
