A method for testing a plurality of integrated circuits. In one embodiment, a plurality of integrated circuits are arranged on a wafer. The integrated circuits are separated on the wafer across the boundary region. Testing interconnects are disposed across the boundary region to test switchable couplings...http://www.google.com.hk/patents/US6380729?utm_source=gb-gplus-share專利 US6380729 - Testing integrated circuit dice
