A DRAM memory cell arrangement having memory cells each having a trench capacitor and a fin field-effect transistor or FinFET for addressing the trench capacitor. The memory cells are arranged in cell rows which are offset with respect to one another and are separated from one another by trench insulator...http://www.google.com.hk/patents/US20050196918?utm_source=gb-gplus-share專利 US20050196918 - DRAM memory and method for fabricating a DRAM memory cell
