RAM Built-In Self-Test logic is presented that utilizes a linear feedback shift register (LFSR) to generate data. Preferably, an LFSR is also utilized for address generation during memory self-testing. More than one cycle is implemented with offset of successive data sequences relative to address sequences...http://www.google.com.hk/patents/US5258986?utm_source=gb-gplus-share專利 US5258986 - Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories
