A method of HDL simulation is described, which may enhance HDL simulation accuracy by allowing a simulator to process a negative setup time and/or hold time. For an electronic circuit device negative setup time and/or a negative hold time, a simulation may be executed without altering the negative setup...http://www.google.com.hk/patents/US7213222?utm_source=gb-gplus-share專利 US7213222 - Method of HDL simulation considering hard macro core with negative setup/hold time
