Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals...http://www.google.com.hk/patents/US8104012?utm_source=gb-gplus-share專利 US8104012 - System and methods for reducing clock power in integrated circuits
