A method of testing a memory device having two arrays of memory cells arranged in rows and columns. Sense amplifiers for respective columns are shared by the arrays, with the sense amplifiers being selectively coupled to the digit lines of respective columns in each array by respective isolation transistors....http://www.google.com.hk/patents/US6167541?utm_source=gb-gplus-share專利 US6167541 - Method for detecting or preparing intercell defects in more than one array of a memory device
