A microprocessor architecture that includes capabilities for locking individual entries into its integrated instruction cache and data cache while leaving the remainder of the cache unlocked and available for use in capturing the microprocessor's dynamic locality of reference. The microprocessor also...http://www.google.com.hk/patents/US5249286?utm_source=gb-gplus-share專利 US5249286 - Selectively locking memory locations within a microprocessor's on-chip cache
