A method for logic design of an integrated circuit IC in which at least one parameter concerning wiring line capacitances is used. The parameter can be precisely estimated even at a logic design stage preceding a layout design stage. The estimation is carried out by, first, classifying the logic units...http://www.google.com.hk/patents/US4823278?utm_source=gb-gplus-share專利 US4823278 - Method of logic design of integrated circuit
