A reading circuit for a multibit memory cell in a memory array, the memory cell having a threshold gate voltage within a range of one of a first, second, third and fourth predetermined threshold voltages corresponding respectively to one of four states of two bits stored in the memory cell. The reading...http://www.google.com.hk/patents/US6178114?utm_source=gb-gplus-share專利 US6178114 - Sensing apparatus and method for fetching multi-level cell data
