A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i.e., a first redundant column is divided into four segments consisting of row block <0,1>,...http://www.google.com.hk/patents/US6307795?utm_source=gb-gplus-share專利 US6307795 - Semiconductor memory having multiple redundant columns with offset segmentation boundaries
