An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second...http://www.google.com.hk/patents/US7840630?utm_source=gb-gplus-share專利 US7840630 - Arithmetic logic unit circuit
