A memory device is disclosed which includes a plurality of memory cells formed in rows and columns. Each memory cell includes a Frohmann-Bentchkowsky p-channel memory transistor and an n-channel MOS access transistor. A plurality of page lines are utilized to contact each memory transistor, while a plurality...http://www.google.com.hk/patents/US6081451?utm_source=gb-gplus-share專利 US6081451 - Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages
