A digital system and method of operation is provided in which several processors (590n) are connected to a shared cache memory resource (500). A translation lookaside buffer (TLB) (310n) is connected to receive a request virtual address from each respective processor. A set of address regions (pages)...http://www.google.com.hk/patents/US20030101320?utm_source=gb-gplus-share專利 US20030101320 - Cache with selective write allocation
