System and method for selective memory module power management

1. A memory system, comprising:

a memory controller;

a memory bus operably coupled with the memory controller to communicate memory commands from the memory controller and communicate memory output signals to the memory controller; and

a plurality of memory modules operably coupled with the memory bus, the memory modules generating the memory output signals and responsive to the memory commands, at least some of the memory modules comprising:

an insulative substrate supporting a system interface;

a plurality of memory devices disposed on the insulative substrate;

a memory hub disposed on the insulative substrate and operably coupled with the memory devices and the system interface, the memory hub managing communications between the memory devices and the system interface in response to memory commands received via the system interface;

an activity sensing device monitoring activity of the memory module containing the activity sensing device in processing memory commands, the activity sensing device being operable to generate an output corresponding thereto; and

a module power controller coupled to the activity sensing device of the memory module containing the module power controller, the module power controller being operable to direct the memory devices in the memory module containing the module power controller to a reduced power state responsive to the output of the activity sensing device indicating activity of the memory module containing the module power controller is not of a desired level.

2. The memory system of claim 1 wherein the module power controller directs the memory module to the reduced power state when the activity sensing device indicates memory module activity has fallen below the desired level.

3. The memory system of claim 1 wherein the module power controller directs the memory module to the reduced power state when the activity sensing device indicates memory module activity has exceeded the desired level.

4. The memory system of claim 1 wherein the module power controller is operable to determine when the memory module should be directed to the reduced power state responsive to the output of the activity sensing device.

5. The memory system of claim 1 wherein the module power controller is operable to direct the memory module to the reduced power state upon receiving an external reduced power signal.

6. The memory system of claim 1 wherein the module power controller of one of the memory modules comprises a master power controller, the master power controller receiving the output of the activity sensing device from at least one other memory module and, responsive to the output of the activity sensing device indicating activity of the memory module is not of the desired level, generates an external reduced power signal to direct the at least one other memory module to the reduced power state.

7. The memory system of claim 1 wherein the memory controller comprises a master power controller, the master power controller receiving the output of the activity sensing device from at least one other memory module and, responsive to the output of the activity sensing device indicating indicating activity of the memory module is not of the desired level, generates an external reduced power signal to direct the at least one other memory module to the reduced power state.

8. The memory system of claim 1 wherein the memory module is directed to the reduced power state by the module power controller responsive to a single indication the activity of the memory module is not of the desired level reflected in the output of the activity sensing device.

9. The memory system of claim 1 wherein the memory module is directed to the reduced power state by the module power controller responsive to a plurality of indications the activity of the memory module is not of the desired level reflected in the output of the activity sensing device.

10. The memory system of claim 1 wherein the memory module is directed to the reduced power state by the module power controller when the output of the activity sensing device indicates the memory module has not received a desired number of memory commands for a predetermined time period.

11. The memory system of claim 1 wherein the activity sensing device comprises an activity monitor that monitors memory commands directed to the memory module.

12. The memory system of claim 11 wherein the activity monitor monitors the memory commands received via the system interface.

13. The memory system of claim 11 wherein the activity monitor comprises part of the memory hub.

14. The memory system of claim 1 wherein the activity sensing device comprises a temperature sensor wherein the temperature sensor is operable to measure when the activity of the memory module is not of the desired level by monitoring temperature.

15. The memory system of claim 14 wherein the temperature sensor is operably coupled with at least one memory device to measure a memory device operating temperature.

16. The memory system of claim 14 wherein the temperature sensor is operably coupled with each of the memory devices to measure an aggregate memory device temperature.

17. The memory system of claim 14 wherein the temperature sensor is operably coupled with the insulative substrate to measure a memory module operating temperature.

18. The memory system of claim 14 wherein the temperature sensor is operably coupled with the memory hub to measure a memory hub operating temperature.

19. The memory system of claim 14 wherein the temperature sensor further comprises an ambient temperature sensor so that a measured temperature of the memory module can be compared to an ambient temperature.

20. The memory system of claim 1 wherein the plurality of memory devices comprise a plurality of DRAM devices.

21. The memory system of claim 20 wherein the reduced power state comprises a reduced refresh state in which memory cells of the DRAM devices are refreshed less frequently.

22. The memory system of claim 21 wherein the reduced refresh state comprises a self-refresh state.

23. The memory system of claim 1 wherein the reduced power state is a reduced response mode in which the module power controller limits response of the memory module to memory commands to control power consumption by the memory module.

24. The memory system of claim 23 wherein the module power controller limits the response of the memory module to memory commands by mandating idle intervals between responses to memory commands by the memory module.

25. The memory system of claim 1 wherein the output of the activity sensing device communicates that the memory devices of the memory module currently store no programming instructions and data, and the power management controller causes a plurality of devices of the memory module to be powered off.

26. The memory system of claim 1 wherein the output of the activity sensing device communicates that the memory devices of the memory module currently store programming information that has not been accessed by the system for an extended period, and the power management controller causes the contents of the memory devices to be saved to a storage device and a plurality of devices of the memory module to be powered off.

27. A computer system, comprising:

a processor;

an input device, operably connected to the processor, allowing data to be entered into the computer system;

an output device, operably connected to the processor, allowing data to be output from the computer system; and

a memory system, operably coupled with the processor, the memory system comprising:

a memory controller;

a memory bus operably coupled with the memory controller to communicate memory commands from the memory controller and communicate memory output signals to the memory controller; and

a plurality of memory modules operably coupled with the memory bus, the memory modules generating the memory output signals and responsive to the memory commands, at least some of the memory modules comprising:

an insulative substrate supporting a system interface;

a plurality of memory devices disposed on the insulative substrate;

a memory hub disposed on the insulative substrate and operably coupled with the memory devices and the system interface, the memory hub managing communications between the memory devices and the system interface in response to memory commands received via the system interface;

an activity sensing device monitoring activity of the memory module containing the activity sensing device in processing memory commands, the activity sensing device being operable to generate an output corresponding thereto; and

a module power controller coupled to the activity sensing device of the memory module containing the module power controller, the module power controller being operable to direct the memory devices in the memory module containing the module power controller to a reduced power state responsive to the output of the activity sensing device indicating activity of the memory module containing the module power controller is not of a desired level.

28. The computer system of claim 27 wherein the module power controller directs the memory module to the reduced power state when the activity sensing device indicates memory module activity has fallen below the desired level.

29. The computer system of claim 27 wherein the module power controller directs the memory module to the reduced power state when the activity sensing device indicates memory module activity has exceeded the desired level.

30. The computer system of claim 27 wherein the module power controller is operable to determine when the memory module should be directed to the reduced power state responsive to the output of the activity sensing device.

31. The computer system of claim 27 wherein the module power controller is operable to direct the memory module to the reduced power state upon receiving an external reduced power signal.

32. The computer system of claim 27 wherein the module power controller of one of the memory modules comprises a master power controller, the master power controller receiving the output of the activity sensing device from at least one other memory module and, responsive to the output of the activity sensing device activity of the memory module is not of the desired level, generates an external reduced power signal to direct the at least one other memory module to the reduced power state.

33. The computer system of claim 27 wherein the memory controller comprises a master power controller, the master power controller receiving the output of the activity sensing device from at least one other memory module and, responsive to the output of the activity sensing device indicating activity of the memory module is not of the desired level, generates an external reduced power signal to direct the at least one other memory module to the reduced power state.

34. The computer system of claim 27 wherein the memory module is directed to the reduced power state by the module power controller responsive to a single indication activity of the memory module is not of the desired level reflected in the output of the activity sensing device.

35. The computer system of claim 27 wherein the memory module is directed to the reduced power state by the module power controller responsive to a plurality of indications activity of the memory module is not of the desired level reflected in the output of the activity sensing device.

36. The computer system of claim 27 wherein the memory module is directed to the reduced power state by the module power controller when the output of the activity sensing device indicates the memory module has not received a desired number of memory commands for a predetermined time period.

37. The computer system of claim 27 wherein the activity sensing device comprises an activity monitor that monitors memory commands directed to the memory module.

38. The computer system of claim 27 wherein the activity monitor monitors the memory commands received via the system interface.

39. The computer system of claim 27 wherein the activity monitor comprises part of the memory hub.

40. The computer system of claim 27 wherein the activity sensing device comprises a temperature sensor wherein the temperature sensor is operable to measure when the activity of the memory module is not of the desired level by monitoring temperature.

41. The computer system of claim 40 wherein the temperature sensor is operably coupled with at least one memory device to measure a memory device operating temperature.

42. The computer system of claim 40 wherein the temperature sensor is operably coupled with each of the memory devices to measure an aggregate memory device temperature.

43. The computer system of claim 40 wherein the temperature sensor is operably coupled with the insulative substrate to measure a memory module operating temperature.

44. The computer system of claim 40 wherein the temperature sensor is operably coupled with the memory hub to measure a memory hub operating temperature.

45. The computer system of claim 40 wherein the temperature sensor further comprises an ambient temperature sensor so that a measured temperature of the memory module can be compared to an ambient temperature.

46. The computer system of claim 27 wherein the plurality of memory devices comprise a plurality of DRAM devices.

47. The computer system of claim 46 wherein the reduced power state comprises a reduced refresh state in which memory cells of the DRAM devices are refreshed less frequently.

48. The computer system of claim 47 wherein the reduced refresh state comprises a self-refresh state.

49. The computer system of claim 27 wherein the reduced power state is a reduced response mode in which the module power controller limits response of the memory module to memory commands to control power consumption by the memory module.

50. The computer system of claim 27 wherein the module power controller limits the response of the memory module to memory commands by mandating idle intervals between responses to memory commands by the memory module.

51. The computer system of claim 27 wherein the output of the activity sensing device communicates that the memory devices of the memory module currently store no programming instructions and data, and the power management controller causes a plurality of devices of the memory module to be powered off.

52. The computer system of claim 27 wherein the output of the activity sensing device communicates that the memory devices of the memory module currently store programming information that has not been accessed by the system for an extended period, and the power management controller causes the contents of the memory devices to be saved to a storage device and a plurality of devices of the memory module to be powered off.

53. A method of controlling power used in a plurality of memory modules associated with a system, each of the memory modules containing a plurality of memory devices, the method comprising:

individually measuring activity in each of the memory modules in response to memory commands from the system in at least some of the memory modules;

determining within each of the memory modules when each of the respective memory modules is inactive based on lack of activity in response to nonrefresh memory commands from the system measured in the respective memory modules; and

internally directing the memory devices in at least one of the memory modules into a reduced power state when it is determined that activity of that memory module is not of a desired level.

54. The method of claim 53 wherein the memory module activity has fallen below the desired level.

55. The method of claim 53 wherein the memory module activity has exceeded the desired level.

56. The method of claim 53 wherein evaluating whether the memory module should be directed into the reduced power state and directing the module into the reduced power state occurs within the memory module.

57. The method of claim 53 wherein evaluating whether the memory module should be directed into the reduced power state and directing the module into the reduced power state occurs in an outside control device outside the memory module responsive to activity of the memory module not of the desired level reflected in the output of the activity sensing device.

58. The method of claim 57 wherein the outside control device resides in a memory controller.

59. The method of claim 57 wherein the outside control device resides in a system controller.

60. The method of claim 57 wherein the outside control device resides in a master memory module.

61. The method of claim 57 wherein the outside control device for other memory modules resides within the memory module.

62. The method of claim 53 wherein evaluating whether the memory module should be directed into the reduced power state is responsive to a single occurrence of activity of the memory module not of the desired level reflected in the output of the activity sensing device.

63. The method of claim 53 wherein evaluating whether the memory module should be directed into the reduced power state is responsive to a plurality of occurrences activity of the memory module not of the desired level reflected in the output of the activity sensing device.

64. The method of claim 53 wherein evaluating whether the memory module should be directed into the reduced power state is responsive to activity of the memory module not of the desired level reflected in the output of the activity sensing measured over a predetermined time period.

65. The method of claim 64 wherein activity is measured via a memory hub of the memory module.

66. The method of claim 53 wherein evaluating whether the memory module should be directed into the reduced power state is responsive to monitoring temperature within the memory module.

67. The method of claim 66 wherein evaluating whether the memory module should be directed into the reduced power state is responsive to monitoring temperature of a memory device within the memory module.

68. The method of claim 66 wherein evaluating whether the memory module should be directed into the reduced power state is responsive to monitoring temperature of each of the memory devices within the memory module.

69. The method of claim 66 wherein evaluating whether the memory module should be directed into the reduced power state is responsive to monitoring temperature of an insulative substrate within the memory module.

70. The method of claim 66 wherein evaluating whether the memory module should be directed into the reduced power state is responsive to monitoring temperature of a memory hub.

71. The method of claim 66 further comprising measuring an ambient temperature in comparison with temperature monitored within the memory module.

72. The method of claim 53 wherein the plurality of memory devices comprise a plurality of DRAM devices and the reduced power state comprises a reduced refresh state in which memory cells of the DRAM devices are refreshed less frequently.

73. The method of claim 72 wherein the reduced refresh state is a self-refresh state.

74. The method of claim 53 wherein the reduced power state is a reduced response mode in which the module power controller limits response of the memory module to memory commands to control power consumption by the memory module.

75. The memory module of claim 74 wherein the module power controller limits the response of the memory module to memory commands by mandating idle intervals between responses to memory commands by the memory module.

76. The method of claim 53 wherein the reduced refresh state is powering off a plurality of devices of the memory module when the activity measured no programming instructions and data are stored on the memory module.

77. The method of claim 53 wherein the reduced refresh state is powering off a plurality of devices of the memory module programming information stored on the memory module has not been accessed by the system for an extended period, the contents stored in the memory module are saved to a storage device and a plurality of devices of the memory module are powered off.

78. A memory system, comprising:

a memory controller;

a memory bus operably coupled with the memory controller to communicate memory commands from the memory controller and communicate memory output signals to the memory controller; and

a plurality of memory modules operably coupled with the memory bus, the memory modules generating the memory output signals and responsive to the memory commands, at least some of the memory modules comprising:

an insulative substrate supporting a system interface;

a plurality of memory devices disposed on the insulative substrate;

a memory hub disposed on the insulative substrate and operably coupled with the memory devices and the system interface, the memory hub managing communications between the memory devices and the system interface in response to memory commands received via the system interface;

an activity sensing device monitoring activity of the memory module containing the activity sensing device in processing memory commands, the activity sensing device being operable to generate an output corresponding thereto; and

a module power controller coupled to the activity sensing device of the memory module containing the module power controller, the module power controller being operable to direct the memory module containing the module power controller to a reduced power state responsive to the output of the activity sensing device indicating activity of the memory module containing the module power controller is not of a desired level, the module power controller being operable to direct the memory module containing the module power controller to a reduced power state by limiting the response of the memory module to memory commands.

79. The memory system of claim 78 wherein the module power controller limits the response of the memory module to memory commands by mandating idle intervals between responses to memory commands by the memory module.

80. A computer system, comprising:

a processor;

an input device, operably connected to the processor, allowing data to be entered into the computer system;

an output device, operably connected to the processor, allowing data to be output from the computer system; and

a memory system, operably coupled with the processor, the memory system comprising:

a memory controller;

a memory bus operably coupled with the memory controller to communicate memory commands from the memory controller and communicate memory output signals to the memory controller; and

a plurality of memory modules operably coupled with the memory bus, the memory modules generating the memory output signals and responsive to the memory commands, at least some of the memory modules comprising:

an insulative substrate supporting a system interface;

a plurality of memory devices disposed on the insulative substrate;

a memory hub disposed on the insulative substrate and operably coupled with the memory devices and the system interface, the memory hub managing communications between the memory devices and the system interface in response to memory commands received via the system interface;

an activity sensing device monitoring activity of the memory module containing the activity sensing device in processing memory commands, the activity sensing device being operable to generate an output corresponding thereto; and

a module power controller coupled to the activity sensing device of the memory module containing the module power controller, the module power controller being operable to direct the memory module containing the module power controller to a reduced power state responsive to the output of the activity sensing device indicating activity of the memory module containing the module power controller is not of a desired level, the module power controller being operable to direct the memory module containing the module power controller to a reduced power state by limiting the response of the memory module to memory commands.

81. The computer system of claim 80 wherein the module power controller limits the response of the memory module to memory commands by mandating idle intervals between responses to memory commands by the memory module.

82. A computer system, comprising:

a processor;

an input device, operably connected to the processor, allowing data to be entered into the computer system;

an output device, operably connected to the processor, allowing data to be output from the computer system; and

a memory system, operably coupled with the processor, the memory system comprising:

a memory controller;

a memory bus operably coupled with the memory controller to communicate memory commands from the memory controller and communicate memory output signals to the memory controller; and

a plurality of memory modules operably coupled with the memory bus, the memory modules generating the memory output signals and responsive to the memory commands, at least some of the memory modules comprising:

an insulative substrate supporting a system interface;

a plurality of memory devices disposed on the insulative substrate;

a memory hub disposed on the insulative substrate and operably coupled with the memory devices and the system interface, the memory hub managing communications between the memory devices and the system interface in response to memory commands received via the system interface;

an activity sensing device monitoring monitors memory commands directed to the memory module, the activity sensing device being operable to generate an output corresponding to module activity based on the monitored memory commands; and

a module power controller coupled to the activity sensing device of the memory module containing the module power controller, the module power controller being operable to direct the memory module containing the module power controller to a reduced power state responsive to the output of the activity sensing device indicating activity of the memory module containing the module power controller is not of a desired level.

83. The computer system of claim 82 wherein the memory module is directed to the reduced power state by the module power controller when the output of the activity sensing device indicates the memory module has not received a desired number of memory commands for a predetermined time period.

84. The computer system of claim 82 wherein the activity monitor monitors the memory commands received via the system interface.