CA1130919A - Vendor control circuit - Google Patents

Abstract

VENDOR CONTROL CIRCUIT
Abstract of the Disclosure A control circuit for a vendor for vending a plurality of items comprising a microprocessor, an electrically alterable memory, a display circuit and an interrogation circuit. Values of parameters, typi-cally prices, associated with the items to be vended are stored in the memory. The interrogation circuit can be activated to retrieve from memory the value of the parameter (e.g., price) associated with any given item. The parameter value is thereupon displayed by the display circuit. The display circuit displays the parameter value retrieved from memory independently of whether the microprocessor has another input equal in value to the value of that parameter. The parameter value stored in the memory for any given item can be altered by the microprocessor.

Description

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VENDOR CONTROL CIP~CUIT
Backqround of the Invention This invention relates to control apparatus and more particularly to a circuit for controlling the functioning of a vendor.
The functions that a vendor is required to perform are becoming so complex that present control circuits, using electro-mechanical means 7 are unduly limited. The typical electro-mechanical control cir-cuit, for example, is severely limited in the number and kind of functions it can perform in response to customer commands~ Also, typical electromechanical control circuits are dedicated to a particular method oE operatioll of the vendor, i.e., they cannot easily be modified to control new vendor unctions or ~o ac~
cept different input signals from the vendorO As a result, when a new vendor function is added to a ven-dor, it is sometimes necessary to make a new control circuit rather than update the existing control cir-cuit alreaday in the vendor. And updating such con-trol circuits usually re~uires additional circuit com-ponents and in~erconnections. In any event, the cost in updating existing control circuits, especially to accommodate increasingly complex vendor functions, can be prohibitive.
Present control circuits also lack means for easily setting prices and for checking that the proper prices have been set. Particularly where the itemsl prices change often, this is a real disadvantage; the .

serviceman or other authori~ed personnel must laboriously change those prices which are to be changed and just as laboriously check all those prices. Likewise, in beverage vendors (for example), other parameters, such as throws o ingredients, are also not easily checked or reset. In addition, prior circuits lack effective means for ~eeping track of the total accumulated sales of a vendor. The total accumulated sales figure, of course, would be very helpful in improving product inventory and cash control.
At least one prototype control circuit using a microprocessor has been developed to address some o~ the above problems. But it also has its disadvantages. The prototype unit, for example, used a volatile memory with a battery backup for storiny prices. Duriny an extended power failure, therefore, the prototype circuit lost the prices. The method o setting prices with the prototype circuit, although an improvement over prior control cir-cuits, has problems o its own. Ana the prototype cir-cuit has no provision for keeping track o total accumu-lated sales.
Summary of the Invention Among various features o the apparatus is the feature that it comprises a memory having a plur-ality o addresses for storing values of at least some of the parameters associated with the items to be vended by the vendor, each item having at least one parameter associated therewith. The parameter values are stored in predetermined memory addresses and are electrically alterable. The apparatus also includes a processor, an interrogation circuit and a display cir-cuit. The processor in response to a plurality oE

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vendor status inputs, memory inputs and control inputs performs arithmetic and logic operations with those inputs and with the values of the parameters associated with the items in a sequence controlled by a pre-selected set of instructions which constitute a program.
The processor supplies output signals based upon the results obtained from the operations to control function-ing of the vendor. The processor can access the pre-determined memory addresses and can alter the parameter ~alues stored therein. The interrogation circuit, which is operable by authorized service personnel, can re-trieve from memory the values of at least some of the parameters stored therein. A parameter value retrieved from memory by the interrogation circuit is visually displayed by the display circuit independently of any other input of the processor being e~ual in value to the parameter value retrieved. As a result, authorized personnel may utilize the interrogation means to retrieve the value of a desired parameter from the memory.
Other features will be in part apparent and in part pointed out hereinafter.
Brief Description of the Drawings Fig. 1 is a front elevation of a vendor with the control circuit of this invention shown connected thereto in bloc~-diagrammatic form;
Fig. 2 is a circuit diagram of a micropro- ~, cessor and master clock used in this invention;
Fig. 3 is a circuit diagram of a chip-selecting logic circuit of this invention;
Fig~ 4 is a circuit diagram showing part of the memory used in this invention;
Fig. 5 is a circuit diagram sho~ing more of the memory used in this invention;

\
~13~9 Fig. 6 is a circuit diagram showing two of the peripheral interface adapters used in this invention; ;
Fig. 7 is a circuit diagram showing the remainder ~ the memory used in this invention;
Fig. 8 is a circuit diagram showing a power sup~
ply for the memory shown on Fig. 7 and reset circuitry used in this invention;
Fig. 9 is a circuit diagram showing the connections among Figs. 2, 4, 10 and 12;
Fig. 10 is a cireuit diayram showing the eonnee-tions among Figs. 5, 9, 11 and 13;
Fig. 11 is a eire~it diagram showing the eonnee-tions among Figs. 6, 10 and 14;
Fig. 12 is a eireuit diagram showing two more of the peripheral interface adapters used in this invention;
Fig. 13 is a eireuit diagram showing an additional peripheral interfaee adapter used in this invention;
Fig. 14 is a circuit diagram showing the remaining peripheral interfaee adapter used in this invention;
Fig. 15 is a circuit diagram showing part of the display cireuit of this invention;
Fig. 16 is a eireuit diagram showing a matrlx of switehes used in setting items and set-ting prices in this invention;
Fig. 17 is a cireuit diagram of an operation mode-setting circuit of this invention;
Fig. 18 is a circuit diagram of a product sensor used in this invention;

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Fig. 19 is a circuit diagram showincJ a wave shaper used in this invention; ~ ~ -Fig. 20 is a circuit diagram of a clocX used as a real time reference in this invention;
Fig. 21 is a circuit diac;ra~ of a delivery door opening circuit used in this inven-tion;
Fig. 22 is a circuit diagram of a dollar bill indicator circuit used in this invention;
Fig. 23 is a circuit diagram of four coin indi-cator circuits of this invention;
Fiy. 24 is a cixcuit diagram of chan~e control circuitry used in this invention;
Fig. 25 is a cixcuit diayram of two circuits us~d in this invention for controlling the dollar escro~
1~ func-tion of a coin handler;
Fig. 26 is a circuit dia~ram of a CREM ènergiza-tion circuit used in this invention;
Fig, 27 is a circui~ diagram of further change control circuitry used in this invention; ,~
Fi~. 2~ is a circuit diagram of two circuits used in this inven-tion to cotrol the functioning oE a bill vali-dator;
FiCJ. 29 i5 a circuit diagram of a free vend cir-cuit oE this invention;
Fig. 30 (sheet 18) is a circuit diagram o~ a display activating circuit of this invention;
Fig. 31 is a circuit diagram of a door lock relay circuit used in this invention;

E~ig. 32 is a circuit diagram of an interloc'~in~
ana sensing circ-lit oE this invention Fig. 33 is a circuit dlagram of a run relly cir-cuit used in this invention;
Fig. 34 is a circuit diayram of an elevator level sensing clrcuit of this invention;
Fiy 35 i~ a circuit diagra~ of elevator control circuitry of this invention for vending a selecte~ item;
Fig. 36 (sheet 18) is a circuit diagram of additional elevator control circui~ry of this invention;
Fiq. 37 is a left-side elevation of the vendor OL
Fig. 1 with a right-~ide ~anel th~reof in an open position to r~e~l a scmi-diclclrammatic represerltation of the control circuitry of this invention;
Fig. 38 is a perspective exploded view, on an en l~rged scale of a part of Fig. 37;
Fig. 39 is a perspective exploded view of an alt~rnative embodiment of the part shown in Fig. 38;
Fig. ~0 is a perspective explodea view of another ~0 alternative embodiment of the part sho~n in Fig. 38;
Fig. 41 (sheet 24) is a left-side elevation o~
the vendor shown in Fig. 1 with parts broken away sho~,~ing an alternative to the parts sho~ in Figs. 38-40;
Fig. 42 (sheet 24) is an enlarged view of a part of Fiy. 41 along line 42--42.
Corresponding reference characters indicate cor--responding parts throughout the several views of the drawings.

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Description of the Preferred Embodiment .
~eferring now to the drawings, first more particuLarly to Fig. 1, there is shown the front of a vendor 1, such as that of the second embodiment of -the vendor disclosed in Canadian Patent No. 1~099,238, which issued April 14, 1981, for vending a plurality of items, indicated collectively by the re~erence num-eral 3 and individually by the reference characters 3a-3x. The vendor 1, as herein illustrated, is an article dispensing vendor, items 3a-3x being items such as food products. It will be understood, how-ever, that the control apparatus of this invention may be applicable to vendors for services, as well as ven- `dors ~or products. Each item has at least one para-meter, e.g., price, associated therewith, the value o which can be varied to vary the functioning of yendor ,' 1. For example, the price parameter of item 3a can be changed from 25¢ to 30~ to vary the amount of money that must be inserted into a coin slot 5 before vendor 1 will vend item 3a. Vendor 1 also has a dollar bill slot 6 for insertion of bills into the vendor.
Vendor 1 includes a control circuit, indi-cated generally at 7, which is the subject of this in-vention. Control circuit 7 includes a memory 9, a microprocessor (MPU) or processing means 11, a plural-ity of selection switches 13, designatea individually by the reference characters 13a-13x, corresponding to items 3a-3x in vendor 1, and a display circuit 15 which includes two displays 15a and 15b. The keys of switches 13a-13x are shown on Fig. 1. The switches are 19 ' '' shown schematically and individually labeled on Fig. 1~.
Switches 13 are not individually labeled on Fig. 1 because of the scale of the figure. However, it can be seen on Fig. 1 that switches 13 are arranged in exactly the same configuration as items 3a-3xf i.e., in a 6 x 4 matrix.
Pressing the switch in the upper left-hand corner of the switch 13 matrix selects the upper left-hand corner item 3, i.e.j item 3a. For the customer's convenience, each item 3 has two tags below it which have printed thexeon a switch key reference character or characters for that item and the price. These tays for item 3a are indicated by the refer-en~e charackers 4a and 4b. These switch k~y reference characters and the prices are no-t shown on Fig. 1 because of the scale of the figure. But, as an example, tag 4a might have printed thereon the reference characters Al and tag 4b might have printed thereon the price $0.30. Of course, the upper left-hand corner switch key would in this example have imprinted thereon the reference character Al.
Memory 9, as is explained in detail below, con-tains RAM, ROM and EAROM memory sections, and has a plural-ity of addresses, e.g., in EAROM, for storing values of at least some of the parameters, e.g., the prices of items 3a-3x, in predetermined memory addresses. The parameter values are stored in EAROM so that they are electxically alterable, i.e., the values can be changed electrically by microprocessor 11. Of course they could also be s-tored in another type of electrically alterable memory, such as R~M.

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MPU ~i.e., processing means) 11 is responsive to a plurality of vendor status inputs, indicated in simpli-fied form by a line Ll from vendor 1 to MPV 11, a plurality of inputs from memory 9, indicated in slmplified form by a line L3 from memory 9 to MPU 11, and a plurality of con-trol inputs, indicated in simplified form by a line LS from switches 13 to MPU 11 and by line Ll. The precise nature :
of these various inputs is explained ~infra in the descrip--tion of the detailed circuit diagram of control circuit 7.
Microprocessor 11 performs arithmetic and logic opexations :
with the above-mentioned inputs and with the values of the parameters associated with items 3 in a sequsnce con-trolled by a preselected set of instructions which constitute a program, a copy of which is attached to this application as Appendix A. MPU 11 supplies output signals, represented in simplified form by a line L7, to vendor 1 based upon the results obtained from the above-mentioned operations to control.the functioning of vendor 1. MPU 11 can also access the predetermined memory locations in memory 9 and alter the parameter values stored therein. It will be understood that khe inputs and outputs of MP~ 11 are represented by single lines on Fig. 1 for the convenience of the reader and that actually, as will become clear below, microproces-sor 11 has a plurality of input lines which accept a variety of input signals from vendor 1 and the rest of control cir-cuit 7. Also not shown on Fig. 1 are a plurality of peripheral interface adapters (PIAs) which interface MPU 11 with vendor 1 and the rest of control circuit 7.

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Switches 13a-13x constitute in~errogation means, operable by authorized personnel such as a serviceman, for retrieving from memory 9 the values of at least some of the parameters stored therein, as is explained in detail infra. Once a parameter value is retrieved from memory 9 it is displayed by display circuit 15 and display 15a.
Specifically, display circuit 15 constitutes means for visually displaying a parameter value retrieved from mem-ory 9 independently of any other input of microprocessor 11 being equal in value to the parameter value retrieved.
For example, if item 3b costs 30~ and the interrogation means (i.e., switch 13b) retrieves the price of item 13b from memory 9, display circuit 15 displays 30¢ in display 15a whether or not thirty cents h~s actually been deposited in vendor 1, i.e., whether or not MPU 11 has a vendor status input representing the deposit of thirty cents in vendor 1.
Referring now to Fig. 2, there is shown micro-processor 11 having a plurality of address lines A0-A15, a plurality of data lines D0-D7, a read/write line R/W, a valid memory address line VMA, a reset line RESET, and an interrupt request line IRQ. MPU 11 is a MC6300 type 8-bit microprocessor sold by ~otorola, Inc. of Phoenix, Arizona. The pin numbers of microprocessor 11 are shown on Fig. 2 on the body of the microprocessor. Pins 7, 35 and 38 and address lines A14 and ~15 are not used in the present embodiment of the invention. Pins 1 and 21, the source supply voltage (V ) inputs, and pin 39, which i5 a three-state control input TSCI are directly connected to dc circuit ground.

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1~31~19 A non-maskable interrupt input oE microprocessor 11, designated NMI, is connected to a connector PF and through a 3~3K resistor Rl to a -~5V power supply. The NMI
input can be used to initiate a program sequence to store 1, relevant data in case of a power failure. Many circuits could be implemented to perform this function, but no specific one is shown in the Figs. Rather, Fig. 8 simply shows two blocks Xl and X2 for performing this function.
Such a power failure circuit is not part of the present invention.
It will be understood that connector PF can equivalently be replaced by a wire connec-ting the two parts thereoE. The purpose in using connector PF, and other connectors described below, is solely to simplify the schematic of control circuit 7 for the convenience of the reader. A connector having two parts is thus another representation of a wire running between the two points in control circuit 7 where the connector is attached. Like-wise a three-part connector is just another representation o a wire or wires directly connecting the indicated three parts of control circuit 7.
Also to simplify the schematic, the chlp-select inputs of the various integrated circuit chips which are described below are specifically labeled but the other in-puts and outputs of those chips are not generally labeledexcept by pin number. Pin assignment charts for the various chips used in control circuit 7 can be found immediately preceding the claims.

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Pins 2 and 8 of MPU 11 are connected to a -~SV
power supply. Pin 2 is a halt input llALT which ~ould influence operation of microprocessor 11 only if it were Low. (The MC6800 microprocessor opera-tes at TTL voltage levels. Accordingly, hereinafter unless otherwise s-tated, Hi~h means a voltage level of around 5 Volts and Low means a voltage level of around 0 Volts.) The collector supply voltage V is supplied to microprocessor 11 by pin 8.
Pins 3, 36 and 37 of microprocessor 11 are sup-plied with ~1 and ~2.nonoverlapp.ing clock signals as re-quirecl from a Motorola MC6875 type clock 17. The pin numbers of cl~cX 17 are shown on its body. Pins 1 and

2 are connected to a kimin~J circuit consis-tinc3 o~ a 150 resistor R3, a lK potentiometer Kl and a 68pF capac.itor Cl which determine the frequency of clock outputs ~1 and 02. Pin 7 is the Bus ~2 output of clock 17. It provides a dri~e output nominally in phase with clock output ~2 on a line L9 to a chip-select circuit indicated ~enerally at ~9 (Fig. 3) and moxe specifically to a NAND gate ~1 in chip~sele~t circuit 19~
Pin 14 of clock 17 supplies a power-on reset signal through a connector PE to a circuit, described infra, which ini~iates a power-on rese-t cycle of control circuit 7.
The other pins of clock 1.7 are attached as shown in Fig. 2 2~ to ensure proper operation of the clock.
Memory 9 includes three Motorola MC68708:L type xead-only memory chips designated by the reference characters ROM1 (Fig. 4), ROM2.(Fig. 4) and ROM3 (Fig. 5). ~I.so shown ~3(~9:~

on Fiy. 5 is a Motorola MC6810A type random~access memory chip RAMl, which is also part of memory 9. Memory chips ROMl - ROM3 and RAMl are directly addressable by micro-processor 11. Memory 9 also includes two electrically alterable read-only memory chips, General Instruments type E~2050, designated by the reference characters EAROMl and EAROM2 (Fig. 7) which are not directly addressable by micro-processor 11.
Control circuit 7 includes six PIAs designated by the reference characters PIAl ~Fig. 6), PIA2 (Fig. 12~, PIA3 (Fig. 12), PI~4 (Fig. 13), PIA5 (Fig. 14), anci PIA6 (Fig. 6). All six PIAs are Motorola type MC6820 peripheral interface adapter in-tegrated circuit chips. PIAs PIAl and PIA6 interface memory chips EAROMl and EAROM2 with MPU 11.
It will be understood that the number of PIAs and memory chips used will vary depending upon the desired capabilities of control circuit 7 and the architecture used in designing control circuit 7. Chip EAROM2, for example, need not be present unless chip EAROMl has insufficient memory capacity for the design at hand.
In addition to being the interface between micro-processor 11 and EAROMl, the PIAs also interface the micro-processor with the vendor status inputs, described in detail infra, and the control inputs such as those rom selection switches 13. All inputs to and outputs from microprocessor 11, except thoseto and from the aorementioned directly ad-dressable memory chips, go through one of the PIAs. Thus, each PIA constitutes peripheral interface adapter means for interfacing microprocessor ll and the inputs thereto.

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Each PIA has eight data pins (pins 33-26) con-nected to the corresponding data lines of MPU 11. Data is transferred between the microprocessor and the PIAs in both directions by means of these pins. Similarly, the ROMs have eight data pins (pins 9-11, 13-17) connected to the corresponding data lines of MPU 11 by means of which MPU 11 reads data from the ROMs. The da~a pins of chips ROMl and PIA2 are connected to the corresponding MPU 11 data lines by eight lines DOa, Dla, D2a, D3a, ~4a, D5a, D6a and D7a. Chip ROMl is also connected to MPU 11 acldress lines AO-A9 by ten lines AOa-A9a which are connected to the address pins of chip ROMl, i.e., pins 1-~, 22-23. B~ means of address lines AO-A9 and lines AOa-A9a, MPUll can address all 1024 bytes in chip ROMl. Lines AOa and Ala are also connected to pins 35 and 36 of chip PIA2.
The data pins of chips ROM2 and PIA3 are connected to data lines DO-D7 of MPU 11 by eight lines DOb-D7b, and the address pins of chips ROM2 are connected to address lines AO-A9 by ten lines AOb-A9b. Pins 35 and 36 of chip PIA3 are also connected to lines AOb and Alb. Chip ROM3 is con-nected to the MPU data lines by eight lines DOc-D7c and to address lines AO-A9 by ten lines AOc-A9c.
- Chip RAMl has only 128 bytes of memory, so only seven address pins are required. Address lines AO-A6 are connected to the address pins (pins 17-23) of chip RAMl by seven lines AOd-A6d. Pin 15 of chip RAMl, a chip select pin, is connected to address line A7 by a line A7d. Lines AOd and Ald are also connected to pins 36 and 35 of chip PIA4. The data pins of chips PIA4 and RAMl (pins 2-9) are connected to data lines DO-D7 by eight lines DOd-D7d.

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Data lines D0-D7 are connected to the data pins of PI~s PIAl, PIA5 and PXA6 by eight lines DOe D7e. Pins 35 and 36 of these PIAs are connected to address lines A0 and Al by two lines ~0e and Ale.
Microprocessor 11 has only a limited number of address lines for addressing all the PIAs and memory chips.
It can uniquely address each chip, however, since e~ch chip has one or more chip-select inputs. For example, each PI~
has three chip-select inputs, designated CS0, CSl and ~
which are used to select that PIA~ For a PIA to be selected, the voltages of its CS0 and CSl inputs must be High and the voltage ~t its CS2 input must ~e Low. In accordance with convent.ion, a chip-select input desi~nation has no bar if the voltage at that input must be H.igh for its chip to be .15 selected, and it has a bar if the voltage at that input must be Low for its chip to be selected. For example, des.ignating two chip-select inputs as CSl and CS2 means that for that chip to be selected the voltage at the CSl input must be Low and the voltage at the CS2 input must be Eligh. Likewise the various memory chips have -thei.r own chip-select inputs. Memory chips ROMl-ROM3 each have a chlp-select input, designated generically by the reference char-acter CS, at pin 20. A Low on pin 20 o one o these chips, .. there~ore, selects that particular chip. Me~ory chip RAMl 2~ has six chip-select inputs, CS0, CSl, CS2, CS3, CS4, and CS5. And pin 27 of memory chips EAROM 1 and EAROM 2 is a chip-select inpu~ CS.

~13~919 MPU 11 does not directly address all the chip-select inputs of the various chips. Instead, it supplies signals on address lines ~10-~13 to chip--select circuit 19 (Fig. 3) which constitutes means for supplying activating signals, i.e., Highs and Lows as recluired, to at least some of the chip-select inputs, including some of the chip-select inputs o~ the PIAs. For example, if the microprocessor wishes to select chip PIAl, it causes address lines A3 and A12 to be High and line A13 to be Low. The Low on line A13 is supplied to an inverter 21 in chip-select circuit 19 ~Fig. 3). The resulting High output of inverter 21 is sup-.lied on a line I,ll to a N~NI~ ya-te G3 (Pig. 2). Likew.ise th~ High on line A12 is supplied to an inverter 23 in chip-sel~ct circuit 19, which supplies the resulting Low to another inverter 25. The resulting ~Iigh output of inver-ter 25 is supplied on a line L13 to the other input of gate G3 .
cau~ing its output to be Low. This Low oukput o~ gate G3 is supplied through a connector PD to pin 23, the CS2 inputJ
of chip PI~l (Fig. 6). The High on line A3 is supplied ~0 directly to pin 22, the CS0 input, of chip PIAl. Since the C51 in~ut, pin 24, is connected through a 3.3K resistor ~5 to a ~5V source, it is also High and chip PIAl is selected.
Of course, the PIAs also need a ~iming slgnal sup- -plied to their enable (E) inputs ~pin 25). This timing sig-nal is supplied from the VMA output line of microp.rocessor11 and the Bus 02 output o~ clock 17 (Fig. 2~. Speci~ically these two outputs are supplied, on line Vl~A and line L~, to gate Gl (Fig. 3) which in turn supplies a composite outpu-t ' (i.e., a Low output if and only if both inputs are ~igh at the same time, otherwise a H.igh output)to a NAND gate G5 wi.red as an inverter. Gate G5 has a ~licJh output, therefore, when the si~nals on lines V~ and L9 are both High. The output of yate G5, which is the desired timing signal, is supplied through a connector PB to the enable (E) inputs (pin 25) of all the PIAs (Fiys. 6, 12, 13 and 14) by way of two lines L14 and L16.
Microprocessor 11 not only determines which PIA
is selected but also controls -the direction of data transfer between itselE and the selec-ted PXA b~ means oE its read/
w.rite line R/W. The sicJnal on line R/W is supp:l.ied to an inverter 27 (Fig. 3) which supplies its output to a ~econd inv~rter 29. The output of inverter 29, which corresponds in voltage to the signal on line R/W, is supplied through a con~
nector PA (Figs. 3, 6 and 14) to pin 21 oE PIAs prAl and PIA6 and to pin 21 of PIAs PIA2-PIA5 by way oE a line L15. The read/wri-te signal is also supplied from line L15 to a line R/Wl connected -to pin 16 oE chip RAMl, its read/write p.in.
Microprocessor 11 selects chip PXA2 by supplying a Hi~h on address lines A12 and A4 and a Low on address line A13. The High on line A4 is supplied on a line ~17 (Figs.
9 and 12) to the CS0 înput (pin 22) of chlp PIA2. For con venience, the corresponding lines connected to the CSO.inputs o:E chips PXA3 and PIA4 are labeled L17a and ~17b. The CSl inp~ of chip PXA2 is also High because it is connected by a line Ll9 -throuyh a 3.3IC resistor R7 to a -~5V source. It should be noted that the CSl inpu-ts for PX~s PIA3-PIA5 axe 1~ .

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also connected to line L19. The High on line A12 and the Low on line A13, as described above, cause the output of gate G3 (Fig. 2) to be Low~ This Low is supplied on a ~ -line L20 to the CS2 input (pin 23) of chip PIA2, thereby selecting chip PIA2. The ~ow on line L20 is also supplied to the CS2 inputs of chips PIA3-PIA5 but it does not cause those chips to be selected in the absence of other address lines being High as described infra.
It should be noted that certain outputs, e.g., the output of gate G3, are connected through a resistor to a ~5V source. These resistors and voltage sources shape the outputs of the components to which they are attachecl.
In the absénce of these wave shaping devices, the waveforms generated by the various components of control circuit 7 could become misshapen due to capacitive effects, which could result in erroneous operation of the control circuit.
Typically the resistors in such combinations have a value of around 3.3K, but that value will depend upon the actual wiring of the circuit.
It is convenient to use hexadecimal notation in writing the addresses of the components of control circuit 7. For example, using binary notation the address of chip PIA2 is 0001 0000 0001 0000, where the value of each bit corresponds to the signal level present on the corresponding address line of microprocessor 11. The hexadecimal address, on the other hand, is 1010. Hereinafter hexadecimal nota-tion is used to describe the signal levels present on address lines A0-A13 unless otherwise noted.

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The address of chip PIA3 is 1020. That of chip PIA4 is 1040, that of chip PIA5 is 1080, and that of chip PIA6 is 1100. Of course, the addresses o~ the PIAs can be changed by simply changing the hard-wi.red connections between them and microprocessor 11. Appendix Ar however, has been written for this particular hard-wired circuit and must be modified in order to function properly with a different hard-wired scheme.
The memory chips are addressed in a similar fashion to the PIAs. For example, the beginning address of ROMl is 2400. That is, the voltage level on address lines A13 and A10 is Hiyh and that on lines All and A12 is Low. Since line A13 i5 Hi.gh, the output of inverter 21 ~Fig. 3) is Low. This Low causes the output of gate G3 (Fig. 2) to be High/ which ensures that none of the PIAs are selected. The output of inverter 21 is also supplied to an inverter 31, the High output of which is supplied on a line L21 to three NAND gates G7, G9 and Gll. NAND
gates G7, G9 and Gll are connected by three lines L23, L25 and L27 to the CS inputs o chips ROM3 (Fig. 5), ROM2 (Fig. 4), and ROMl, respectively. The output of only one o~ these gates will be Low at any one time, therebv selecting its respective :
chip. Which output is Low is determined by the signal levels .
on lines A10 and All. The signals on lines A10 and All are -~
-25 supplied to a number of inverters, dPscribed below, which together with three NOR gates G13, G15 and G17 decode the signals and supply them to NAND gates G7, G9 and Gllo : :

The High voltage on line A10 is supplie~ to an inverter 33 (Fig. 3), and its resulting Low output is sup-plied to NOR cates G15 and G17 and to an inverter 35, causing the latter's output -to be High. This High is supplied to NOR gate G13 and its resulting Low output is supplied to gate G9. This causes its outpu-t to be ~igh, thereby preventing selection o~ memory chip RON2. ~he Low signal on line All is inverted by an inverter 37 and this High signal is then supplied to gates G13 and G15 and to an inverter 39. The High supplied to gate G15 causes its output to be Low. This Low in turn causes the output of yate G7 to be Higll, thereby preventinq selection of memory chip ROM3. The Low output of inverter 39 i5 supplied to gate G17 causing its output to be High, which output is supplied to gate G11. Since all inputs to gate Gll are High, its output is Low, which selects chip ROMl. The selection of chips ROM2 and ROM3 is similar to that of chip ROMl except for.the addresses. The beginning address of chlp ROM2 is 2800, while that of chip ROM3 is 2C00.
ROMs ROM1-ROM3 are used to store the program for MPU 11.
Memory chip RAMl can be addressed by Lows on address lines Al, A12 and A13. The Low on line A7 is sup-plied directly to the CS5 input of chip RAMl (Fig. 5) by way of line A7d. The Low on line A12 is inverted twice (by inverters 23 and 25) and supplied on a line L29 to the CS4 input of chip ~AM1. Likewise, the Low on line A13 is inverted twice (by inverters 21 and 31) and supplied on line L21 and a line L31 to the CS2 input of chip RAM1. The ~1~0~a~9 CSO inpu-t of chip RAMl is connected by way of a line L33 to line L16 (Fig. 13) which carries the enable output from connector PB (Figs. 2 and 3) described above. The CSl input is tied to ground and th~ CS3 input is connected through a _ 5 3 3K resistor R9 to a +5V source. Memory chip RAMl is basically used as a scratchpad for MPU ll.
The prices of items 3a-3x are stored in chip EAROMl and, if necessary, in chip EAROM2 (Fig. 7). The EAROMs are not directly addressable by microprocessor 11. Rather MPU ll addresses the EAROMs and transfers data, e.g., prices, to and from them by means of chips PIAl and PIA6 (Fig. 6). For example, to store some data in chip EAROMl, MPU ll supplies that dat~ on data lines D0-D7 to data lines DOe-D7e (Figs. 6, 11). Data lines DOe-D7e are directly connected to the data pins (pins 26-33) of chips PIAl and PIA6, and so supply the data to those pins. The PIAs in turn supply the da~a to chip EAROM1 over a plurality of lines L35, L37, L39, ... ~ -L65. The address pins of chip EAROM1 (pins 19-23) are con~
nected by five lines A0f-A4f to pins 2-6 of chip PIAl. Pins 25 and 26 of chip EAROMl mode control pins, are connected to pins 7 and 8 of chip PIA1 by two lines L66 and L68~ The data can be supplied to chip EAROM2 by means of two onnectors PG and PH (Fig. 7) connected to lines L35-L65.
The EAROMs require a ~28V regulated power supply which is indicated generally at 41 ~Fig. 8~ and includes a 723 voltage regulator chip from Signetics Corp. of Sunnyvale, California. Also shown on Fig. 8 is reset circui~ry, indi-cated generally at 43, which causes control circuit 7 to 2'2 ~3~9i5;~ :

reset under power-on or malfunction conditions. Vnder power-on conditions, for example, clock 17 ~Fig. 2) sup-plies a low through connector PE (Figs. 2, 8) to an inverter 45. Inverter 45 supplies a High through a lOK resistor Rll to the base of a type 2N2222A transistor Ql, causing it to conduct. A line L67, connected to the collector of tran-sistor Ql, is thereupon brought Low. Line L67 ~Figs. 2, ~, 7, 8, 9, 10, 11, 12, 13, 14) is connectecl to the reset inputs ~pin 34~ of all the PIAs and to the RESET input of MPU 11.
The Low on line ~67, therefore, prepares the PIAs and the microprocessor for operation of control circuit 7.
The circuitry shown on Figs. 2-7, 9-14 is contained on one circuit board, not shown, which must be connected to the remaining circuitry of control circuit 7 shown on Figs.
15-36. This connection is made by means of two plugs, desig-nated by the reference characters Pl and P2 (Figs. 6, 8, 12, 13, 14)~ Referring specifically to Fig. 8, it should be noted that two portions of plug P2 are shown as oblongs while the rest of plug P2 on these Figs. is shown as a rec-tangle whose outline is made up of dashes. The oblong symbolis used, particularly in the remaining Figs., to indicate a single pin connection of a plug. The rectangle is used, on the other hand, to indicate a plurality of such connections.
The number inside the oblong indicates the plug pin number, identical pin numbers, of course, indicating a connection between the two pins. For example, one plug P2 oblong on Fig. 8 con~ains the number 31. This indicates a direct con-nection between that point on Fig. 8 and pin 31 of plug P2 on Fig. 14, which is connected to pin 6 of chip PIA5.

~3~919 : -Display circuit 15, including displays 15a and 15b, is shown in its entirety on Fig. 15. Briefly, display circuit 15 includes a 7447 type BC~~to-seven segment decoder ~
47, seven PNP transistors Q2-Q8, four-digi-t seven-segment - -display 15a, six-digit seven-segment display 15b, and ten inverters 49-58, such as are supplied in an MC1413 type in-verter package. The digits of displays 15a and 15b, as lS
described in detail below, are multiplexed by inverters 49-58~ That is, only one digit of the two displays is acti-va-ted at a given instant, the particular digit activated being determined by the outputs of inverters 49-58.
Fig. lfi shows selecticn switches 13a-13x as well as a set of t~elve price-setting switches 60-71. Switches 60-71, also shown on Figs. 37-38, 41 and 42, are associated with the numerals 1-9, the character "~", the numeral ~lO~
and the character "~"~ respeetively. The numeral switches, i.e., switches 60-68 and 70, are used to enter prices into memory 9. Switch 69, the "*" switch, is a price-loadiny switch, and switch 71, the ll~tll switch, is a display-clearing switch. Also shown on Fig. 16 are two price-rolling switches 73 and 74, which can also be used to enter prices, and a fast-slow switch 75, which is used in conjunction with switches 73 and 74. Except for switch 75, the switches shown on Fig. 16 are arranged in a matrix 76 of eight rows and six columns. Of course, other arrangements of switches could be used, but the program appearing as Appendix A was written for this particular switch matrix. Each row of the switch matrix shown on Fig. 16 is connected through one of a series , ~ . -~L3~9~
' ' of lK resistors, designa-ted by l:he referen~e charac~ers Rll-R18, to a ~12V source and clirec-tly to the OU~pllt of one of a serie, of 7407 type open-collector output: drivers~
designated by the reference numerals 77-84. Each col~nn is connected through ~ne of a series of 10I resis-tors, designated by the reference characters R20-R25, to ground and through one of a series of 220K resistors, designated by the reference characters R27-~32, to a ~OR ~a-te G19 and to one of a series of nonin~erting gates or bu~Ler amplifiers, designated by the xeference characters 86-91.
NOR gate Gl9 (Fig. 1~) is connected by a line ]69 to a mode SettinCJ cil-uit, i~licated generally at ~3 (Ficr.
17). Control circuit 7 has two mutuall~ e~c:Lusive operatioll modes, ~iz., a price-settin~ mocle and a vending rnode. ~ode-, I~ settiny circui-t 93 constit-ltes means for se-~tin~ m~e o operation of control circuit 7. Included in mode-settin~
circuit 93 are two noninverting gates 95 and 97, two NO~ gates G21 and G23 and a mode-setting switch 98. Switch 98 has two contacts 98a and 98b which make up one side thereof. The other side of switch 98 is connected to ground.
Contact 98a is connected through a lK resistor R20 to a +5V source and directly to gate 97 and NOR gate G21.
Contac-t 98b is connected throuyh a lK resistor R21 to a -~5V
source and directly to gate G23. Contact 98a is shown as grounded in Fig. 17, which causes Lows to ~e present at the input to gate 97 and at one input of gate G21. Con-tact 98b, being open, does not ground its input to gate G23, so that input is High and its outpu-t Low. This is the vendi~ng mode position o switch 98. In -the price-setting mode, the blade t , ~3~9i~

of switch 98 contacts contac-t 98b ra-ther than contact 98a, thereby reversing the above voltaye levels.
Fig. 18 shows a produc-t sensing circuit 99 which is part of control circuit 7. Circuit 99 in-cludes two light-emitting diodes (LEDS~ 101 and 103 and two phototransistors Q3 and Q5. When cir.cuit 99 is in-stalled in a vendor such as vendor 1, LED 101 and pho-totransistor Q3 are disposed on one side of a delivery ::
station, said station being indicated generally at 105 (Fig. 1) and LED 103 and phototransistor Q5 are dis- . -posed on the opposite side of delivery station 105. A
product present at the delivery station will interrupt ::
the passage o~ light from the LE~s to at least one of phototransistors Q3 and Q5 causing at least one and of-ten both of the~ to cease conducting. This causes the collector(s) of the nonconducting transistor(s) to go .
High, signalling the presence of an item at delivery ~:~
station 105.
Vendor 1 includes an elevator, not shown, which moves from delivery station 105 to four levels, designated by the reference characters A, B, C and D, on which the items 3 to be dispensed are located.
Once the elevator reaches the desired level, the de-sired item is conveyed onto the elevator and the ele-vator descends to delivery station 105 to complete the vend. The elevator and the apparatus which conveys the desired article onto the elevator are not part of the present invention but are of the type disclosed in Canadian application Patent No. 1,099,238. In that application, the elevator is caused to move up to the desired level by an elevator motor, connected to a 9~19 motion sensor. Such a motion sensor supplies a series of pulses indicative of the speed of the elevator mo~or, the pulses being closer together the faster the motor is turn-ing. When the eleva-tor reaches the proper level, it en-gages a stop, not shown, which prevents further movementof the elevator. At this point, the elevator motor stops and the pulses from the motion sensor cease.
Control circuit 7 includes sensing means, 1ndi- ' cated generally at 106 (Fig. l9), for supplying a vendor status input comprising a series of pulses indicating the speed of rotation of the elevator motor in the vendor to MPU 11. The output of the motion sensor is a train of pulses which is supplied through a 47Q resistor R23 to pins 2 and 6 of a 556-type ~.imer 107 connected to ~unction lS as a wave-shaper. Timer 107 is also called a sp~ed-sensor clock. Timer 107 shapes these pulses and supplies them through a .001~ F capacitor C3 to a noninverting gate 109 and directly to a noninverting gate 111. The outputs of gates 109 and 111 are supplied to MPU 11 through pins 8 and 47 of plug P2.
Control circuit 7 also includes a clock 113 (Fig.
20), called a time-base clock, which constitutes clock means for supplying interrupts to MPU ll at a constant rate which the microprocessor uses to determine if the number of the pulses from sensing circuit 107 fall within a predetermined range. Clock 113 is a 556-type timer with a period of 10 milliseconds. The output of clock 113 (pin

3) is supplied directly to plug P2, pin 48 and through an inverter 115 to plug P2, pin 36.

Vendor 1 includes a delivery door 117 (Fig. 1 in front of delivery station 105 which automatically opens when an item is sensed at delivery station lOS by photo~
transistors 03 and Q5 (Fig. 18). A circuit for causing door 117 to automa-tically open when an item is sensed at the delivery station is shown on Fig. 21. Briefly, MPU 11 causes a High to appear at plug P2, pin 13 when an item is sensed at delivery station 105~ This High is supplied -~
to a noninverting gate 119 which is connected to the base of a NPN transistor Q7. The base of transistor Q7 is also connected through a 1.8K resistor R25 to +5V source. When the output of amplifier 119 goes High, therefore, transistor Q7 conducts caus:ing current to flow through a relay coil 121 from a ~12V source. This closes the contacts of a relay, not shown, which closure in known manner is used to power a motor, remove a latch, etc.,to open door 117.
Control circuit 7 controls the coin-handling functions of vendor 1 such as credit accumulation and coin return. Speciically, it controls the functioning oE a coin handling unit, not shown, and a dollar bill validator, also not shown. Connections to the coin handler and vali-dator are indicated by the reEerence characters CH and VAL respectively. Of course, standard coin handling units and validators must be adapted to be electrically compatible with the voltage levels of the control circuit, but this adaptation can easily be performed by one of ordinary skill in the art and is not part of this invention. When the coin handler or validator detects a valid coln or bill, it generates a signal corresponding to the type of coin or bill detected; the signal for each type coin or bill being a 91~

positive pulse. For example, the positive pulse correspond-ing to a dime is supplied from an optoelectronic source and sensor assembly disposed at the entrance of the dime coins tube in the coin handler.
The pulse signaling the detection of a valid dollar bill is supplied to an indica~or circuit 123 ~Fig.
22) comprising two lK resistors R27 and R29, two lOOK re-sistors R31 and R33, two noninvertlng gates 125 and 127, a O.Ol~F capacitor C5, and a diode D3. The pulse is sensed by gate 125 and then supplied to plug Pl, pin 30. The pulse is also supplied to capacitor C5 which, together with diode D3 ~nd resistor R29, shapes it into a spike which is sensed by gate 127 and supplied to plug Pl, pin 22. These signals supplied to plug Pl are thereafter sup-plied to MPU 11.
In a similar manner, pulses indicating the detec-tion of nickels, dimes, quarters and dollar coins are sup-plied to four identical coin indicator circuits 129 r 131t 133 and 135 (Fig. 23). Indicator circuits 129, 131, 133 and 135 each have a 4.7K resistor ~designated by the refer-ence characters R35, R37, R39 and R41) r a 220K resistor (R43, R45, R47 and R49), a .Ol~F capaci-tor tC7, C9, Cll and C13), a first lOOK resistor ~R51, R53, R55, and R57), a second lOOK resistor (R59, R61, R63, and R65), a first noninvert-ing gate (137, 139, 141 and 143) and a second noninverting gate ~145, 147, 149 and 1511.
The nickel indicator circuit, circuit 129, supplies its pulse (i.e., vendor status input) representative of a !

~, :

deposit of a nickel in vendor 1 -to plu~ Pl, pin 34 and the spike input derived th~rerom to pluq P2, pin 9, ana there~
by supplies it to microprocessor 11. The dime indicator circuit, circuit 131, supplies ~ts pulse and spike outputs indicatincJ the deposi-t of a diMe to plug Pl, pin 33 and plug P2, pin 38. Circuit 133, the quarter indicator cir-cuit, supplies its two outputs to plug Pl, pins 32 and 20.
And the dollar coin indicator circuit, circui~ 135, supplies its output to pins 31 and 25 of plug Pl. In summary, indi~
cator circuits 123, 129, 131, 133 and 135 constitute means for supplying vendor status inputs representative of a de-posit of money in vendor 1 to MPU 11.
Fic~. 2~ shows add:ikional circuitry, indic~ted generally at 153, for con-trollincJ the func-tionin~ o~ the coin handler. Sic~nals from the coin handler indicating empty change tubes are supplied to circui-t 153 over -four lines labeled L71, L73, L75 and L77. IE the nickel chan~e tube in the coin handler is empty, for example, there will be a Low on line L71. Lows on lines L73, L75 and L77 indicate ernpty dime, quarter and dollar coln change tubes respectively. The nickel chancJe tube empty signal is sup-plied to a D-type latch 155. Empty signals for the dime, quarter and`dolla^ coin tubes are supplied to addi~ional D-type latches 157, 159 and 161. The clock inputs of the latches are connectea to a clock 163 comprising a 555-type timer.
- A Low on l~ne L77, si~ni~ying that ~he dollar coin tube is empty, causes the Q output of latch 161 to go Low. This Low QUtpUt is supplied to a noninverting gate 165 connected to plug Pl, pin 28. Similarly, if the dime tube is empty, the Low on line L73 causes the Q output of latch 157 to go Low. This I.ow output is sensed by nonin-verting gate 167 and supplied to plug Pl, pin 27. In re-sponse to the signal levels On pins 27 and 28 of plug Pl being Low, MPU 11 stops using dollar coins and dimes to make change and instead uses nickels and quarters.
The Q outputs of latches 155 and 159 go Low whenever the nickel and quarter change tubes, respectively, are empty. These outputs are supplied to an AND gate G25 causiny its output to go Low, whenever either or both of these tube~ are empty. This Low output is supplied via a noninverting gate 16~ to plug Pl, pin 12. It is also sup-plied to the base of a PNP transistor Q9, causing it to con-duct, thereby lighting an out-of-change indicator lamp 171 connected between the collector of transistor Q9 and a +12V source.
MPU 11 causes the coin handler to make change rom its coin tubes by causing Highs to appear on pins 16-19 of plug Pl. To cause a dollar coin to be returned in change, the MPU puts a High on plug Pl, pin 16. Pin 16 of plug Pl is connected to a voltage divider consisting of a 4.7K resistor R67 connected through a lOK resistor R69 to ground.- The base of an NPN transistor Qll is connected to the voltage divider between the two resistors. The emitter of transistor Qll is also connected to ground, while its collector is connected through a 4.7K resistor P~71 to a ~12V source a A High at pin 16 of plug Pl, therefore, causes transis-tor Qll to conduct, which causes the voltage measured ~13~19 a~ its collector to cJo Low. The collector of transistor 5!11 is connected throuc~h a ~lQ resistor R73 to the base of a P~P transistor Q13, the emitter C.f which is connected to the -L12V source and the collector o~ which is connected by a line L79 to a solenoid, not shown, on the dollar coin -tube in the coin handler. A Low on the collector of transis-tor Q~ causes transistor Q13 to conduct, energizing the~ dollar coin relay solenoid, which causes a dollar coin to be ejected from its coin tube.
A High on pin 17 of plug Pl causes an NPN tran-sistor Q15 to conduct, which in turn causes a PNP transis-tor Q~7 to conduct. q'ransistor Q17 is connected by a 1irl2 L~l to the correspondincJ ~olenold on the quarter change tu~e. When it conducts, that solenoid is energ:ized, causiny a quarter to he ejected ~rom its chan~e tube. In the same way, Highs on pins 18 ana 19 of plu~ Pl cause cur-rent to flow in lines L83 and L85 to energize the solenoids associated with the dime and nickel tubes respectively.
Circuit 153 also includes a PNP transistor Ql~, the collector of which is connected to ground, the base of which is connected to the output oE cloc~ 163 and the emit~
ter o which is connected via a line L87 to a sensor LED
circuit, not shown, in the coin handler. Coin handlers use a plurali-t~ of standard LED sensors to check coin levels.
The clock signal on line L87 is used to pulse the LEDs in those sensors so that they will not remain "on" continuously, overheat and fail. These LEDs are pulsed with relativelY
high current to decrease the possibility of false "Tubes Full" signals being sen-t to MPU 11 because of dust accumula tion on the sensors or the like.

~3~:19 I~ is desirable in coin handlers to na~e an escrow position for ~ollar coins so that if th~ customer chooses not to comple.e a vend, he call recei~t? bac~ the very dollar coins h~ inser~ed into vendor 1. Co~rol circuit 7 has circuits 173 and 175 (FiCJ. 25) ~o- control-ling such escrot~.
Bxiefly, in xesponse to an input si r~l at pin 43 of plug Pl, circuit 173 provides a ground connection on a line L89 to a dollar coin escrow solenoidr not shown, in the coin handler. The o-ther end o~ said s~lenoid is connected to a source of power, so when line ~Z9 provides.
a path to ground the solenoid is activa-ted c~using ~lollar coins ko be trapped in the escrow chute. The coin handler also has a dollar coin return solenoid which deflects the dollar coins stored in the escrow position to the customer when it is activated. Activation of the return solenoid is accomplishea by supplying a signal from MPU 11 to pin 11 of plug 1. This causes a line L91 of circuit 175 to go Low, activating the return solenoid to which it is connected.
~ ~ circuit 177 (Fig. 26), identical ~o circuit 175 in structure ana opera~ion, is used to activa e the CRE~1, not shown, in the coin handler. Briefly, a High on pin 13 of plug Pl causes a line L93 to go Low, providing a ground pat~ for the CRE~I.
~5 Fig. 27 sho~s a circuit 179 used to sisnal the m-~oprocessor tha-t the cus-tomer wants his mo~e~ back. I~
the customer has pressed the coin return swi tC;l to abort the vena, the coin handler supplies a Xigh on a line L94 to circuit 179. This ~ligh is sensed by a bufer or noninverting gate 181 and supplied to pin 20 of plug P2.
As explained in detail infra, MPU 11 in response to this High on pin 20 of plug P2 returns the customer's money if a vend - 5 is not in progress.
The serviceman uses circuit 179 to empty the coin tubes. For this purpose the coin handler includes four switches, not shown f one for each tube. Pressing the nickel tube switch causes a High to be supplied on a line L95 from the coin handler to a buffer gate 183 in circuit 179. The output of gate 183 is connected to pin 46 o pïug Pl. The pressing of the dime tube switch causes a High to appear on a line L97, which is sensed by a buffer gate 185 and supplied to pin 47 of plug Pl. I,ikewise, the High resulting from the pressing of the quarter tube switch is supplied on a line L99 to a buffer gate 187 and from there to pin 48 of plug Pl.
Pressing the dollar coin tube switch causes a High to be sup-plied on a line L101 to a buffer gate 189 and from there to pin 49 of plug Pl. The signals from gates 183, 185, 187 and 2Q 189 are also supplied to a NOR gate G27. Whenever the out-puts of one of these amplifiers is High, the output o gate G27 is Low. This causes the input of an inverter 191 to become Low, so its output goes High. This High output is supplied to pin 1 o F plug Pl. Briefly, the High on pin of plug Pl, called a payout request interrupt, causes MPU 11 to payout coins from the coin tube whose switch has been actuated un-til that switch is released.

. .

~3~91~

The dollar bill validator moves ~ bill into an escrow position after it has been validated and then either accepts the bill by moving it to a storage location, or re-turns the bill to the customer depending upon whether or no-t the vend has been completed or aborted. Control cir- !
cuit 7 controls -the move~ent of the valid bill from the escrow position by means of two identical circuits, desig-nated by the reference numerals 193 and 19S (Fig. 28). To return the dollar bill-to the customer, MPU ll causes pin 15 of plug Pl -to go High. This ~ligh is supplied through a 100K resistor R75 to a noninverting gate 197. The out-put of gate 19, is supplied thxough a lK .~esistor R77 to the ba~e of an NPN transistor Q21, the emitter of which is con-nected to ground and the collec-tor of which is connected by a line L103 to the valid~tor. The High on the base of trallsistor 021 causes line Ll03 to be Low, thereby signal-ing the validator to return the bill. Li~ewise, ~o accept the bill, ~U 11 causes pin 45 of plug Pl -to go High. This results in a line L105 connected to the validator and to the collector of an NPN transistor Q23 to go Low, thereby si~naling the validator to move the bill to the storage position.
On occasion the operator of vendor l may~desire to vend items 3 simply in response to the actuation of se-lection switches 13, i.e., a "free vend". ~his is easily accom~lished by means of a free vend switch l99 (Figs. 29 and 37) having first and second positions. ~ree vend switch 199 has contacts 199a and 199b corresponding respectively ~L3~9 to the first and second positions of -the switch. Contact l99a is connected through a lK resistor R79 to a fl2V source and through a 220K resistor R81 to a buffer gate 201. The output of gate 201 is connected to pin 22 of plug P2.
When free vend switch 199 is in its second position, as shown in Fig. 29, the outpu-t of gate 201 is High. When switch 199 is switched to its first position, however, the +12V source is grounded through the switch, so the output , of gate 201 and the voltage on plug P2, pin 22 are Low.
This Low is subsequently detected by microprocessor 11.
Control circuit 7 keeps track of the total accumu-lated sales igure or vendor 1. This igure is stored in chip R~Ml at address 0037-003A, and is updated a~ter every vend by MPU 11. The total sales igure is also stored ln chip EAROMl at address "lD" and "lE" therein. Six-digit seven-segment display 15b constitutes means for displaying the total accumulated sales figure. Of course the customer has no need to know the total sales igure, so display 15b is normally inactivated and is preferably disposed inside the cabinet of the vendor as shown in Fig. 37. The service-man has a key 203 (Fig. 30) which constitutes serviceman-operable means for activating display 15b. The serviceman merely inserts key 203 in a slot 204 of a sensor 205 in an activating circuit 207 to activate display 15b. -Display 15b is normally inactivated because in-verters 53-58 (Fig. 15) have no way to sink the current ~rom display 15b. Inverters 53-58, being part of an MC1413 type inverter package, require a ground connection in order to sink that current. This ground connection is provided on a 1~L3~
.~

line L107 when key 203 is inserted into sensor 205 (Fig.
30~. Specifically when the serviceman places key 203 in the position in sensor 205 shown in ph~ntom, it breaks the light path between an LED 209 and a ~pho-totransistor Q25 contained therein. This stops conduction of the photo-transistor, causing the voltage measured at its collector to become positive. This positive voltage is sensed by a buffer gate 211 and supplied to the base of an NPN tran-, sistor Q27 in the common-emitter configuration. Transis-tor Q27 conducts, and as a result line L107 goes Low, grounding inverters 53-58 and thereby activating display 15b.
~ he total accumulated sales figure is rese-t to zexo by a switch 213 which constitu-tes means ~or supplying a reset control input signal to MPU 11. When switch 213 is closed by the serviceman or other person wi*h access thereto, it causes the outputs of two buffer gates, designated 215 and 217, to go High. These outputs are supplied to pins 1 and 11 of plug P2 and from there through the PIAs to MPU 11.
Circuit 207 also includes a jumper 2ig which can be removed to prevent inadvertent or non-authorized reset-ting of the total sales figure.
When the elevator is not at delivery station 105, door 117 is locked closed by a solenoid-operated latch, no~
shown. This is a safety feature which prevents a customer from opening door 117 whlle the elevator is moving. It also prevents a customer from surreptitiously removing items irom the lower levels while the elevator is at the higher levels J
e.g., level A. If f however/ the elevator is at delivery .

~L3~

s-ta-tion 105, door 117 is unlocked if there is a product present. This is accomplished by a door lock solenoid circuit 221 (Fig. 31) which energizes solenoid 223 to unlatch door 117 when the elevator is at delivery station 105 and a product is sensed by circuit 99. When MPU 11 has determined that the elevator is at the delivery station, and a product is present, it supplies a High to pin 7 of plug Pl which is connected to a buffer gate 225. The re-, sulting High output of gate 225 causes an NPN transistor Q29 to conduct, energizing solenoid 223 and unlatching and opening door 117.
Control circuit 7 includes an in-terlocking circuit 227 (E`ig. 32) which cons-titutes means for supplying vendor status inputs to MPU 11 which inclicate that vendor 1 is not ready to vend an item 3. Interlocking circuit 227 includes a switch 229 for indicating whether the élevator is at delivery station 105, a switch 231 for indicating whether door 117 is closed, and a switch 233 for indicating whether door 117 is locked. Switch 229 has ~wo contacts 229a and 229b. Its blade is connected to a +12V source. Contac~
229a is connected through a bufer gate 23S to pin 10 of plug P2. Contact 229a is also connected to switch 231. When the elevator is at delivery station 105, switch 229 is closed through contact 229a and thus supplies +12V power to switch 231 and to gate 235 causing its output to be High.
When the elevator leaves delivery station 105, however, switch 229 closes through contact 229b and the output of ga-te 235 goes Low, thereby removing power from switches 231 and 233.

, 915~

Switch 231 is closed ~hen door 105 is closed and open when it is not. When closed, switch 231 connects con-tact 229a through a buffer ~ate 237 to pin 9 of plug Pl.
If the elevator is at the delivery station and door 117 is closed, the output of gate 237 is High. If either or both of these conditions is not met, the output of gate 237 is Low.
Switch 233 is connected to switch 231 and is oper, when door 117 is unlocked. Locking of door 117'closes switch 233, which connects switch 231 through a buffer gate 239 to pin 8 o plug Pl. If the elevator is at delivery station 10~ and door 117 i.s closed and locked, the G~tput oE gate 239 is ~ligh. Otherwise, it is Low.
Normally, when not in the vend cycle, the elevator is at delivery station 105 and door 117 is closed but un-locked. As a result, the normal positions of switches 229, 23I and 233 are as shown in Fig. 32.
If all three switches are closed and conditiGns are proper for a vend, MPU 11 supplies a vend signal on pin 6 of plug Pl to a run relay circuik 241 (Fig. 33) which conskitutes means for initiating vending oE the selected item 3. In response to the vend signal from MPU 11, ~he output of a noninverting gate 243 in circui~ 241 goes High which causes an NPN transistor Q31 to conduct. This energi~es ~ -a re3.ay coil-245 which in the kno~n manner closes a switch, not shown, to suppl~ po~er -to the elevator.

~L~3~91~ ~

Control circuit 7 controls the operation of the elevator and dispensing of items 3 by means of a circuit 247 (Figs. 34-36). Circuit 247 includes six horizontal solenoids (HORSOLs) designated by the reference numerals 249, 251, 253, 255, 257 and 259, each of which is associated with one column of items 3. ~ particular item 3 is moved onto the elevator in response to the elevator being at that item's level and the HORSOL associated wlth that item's - column having been energized before the elevator moves from the delivery station. Control circuit 7 deals only with energizing the proper HORSO~ and stopping the elevator at the proper level. The particular means used to then convey the selected item onto the elevator is not part of this in-vention.
The HORSOLs are connected on one side to one side of a 24 VAC power line, designated LVl, and on the other side through one o a set of six triacs, designated by the refer-ence characters 261, 263, 265, 267, 269 and 271, to the other side, designa-ted LV2, of the power line. Each triac has its own gating circuit, indicated by the reference numerals 273, 275, 277, 279, 281 and 283, all of which are identic~1 When a triac is gated by its gating circuit, its correspond-ing HORSOL is energized. Since ~all the gating circuits are identical, only circuit 273 is described in detail.
To energize HORSOL 249, as is required when the item selected is in the leftmos-t column as shown in Fig- 1 r MPU 11 causes pin 35 of plug Pl -to be High. This High is - supplied to a NAND gate G29 in gating circuit 273. The other input of gate G29 is clock pulses from a clock 285, /~
39i~1 so the output o~ gate G29 is periodically Low. This causes current to flow from a ~12V source throu~h one side of a transformer 287 into ga-te G29, which in turn causes current to flow through the other side of transformer 287 into ~he gate terminal of triac 261. Current tllen flows through the main terminals of triac 261 and HORSO.L 249 is energized.
To vend an item in the second column from the left, ~U 11 energizes HORSOL 251 by causing pin 36 of plug Pl to be High. Likewise Highs on pins 37, 33, 39 and 40 o plug Pl result in HORSOLs 253, 255, 257 and 259 respectively being energized.
The purpo5e o cl.ock 235 is to pre~2nt the trans-~ormers in gatin~ circuits 273, etc., fr~m b~l.rnin~ out as a result of being on for relatively long periods~
Microprocessor 11 controls ',he level at which the elevator stops by means of pins 2-5 of plug Pl (Fi.g. 34).
Pin 2 of plug Pl, which is associated with level A, is con~
nected through a noninverting gate 289 to a switcll 291, the other side of which is connected to a line L109. Pins 3-5 are connected in exactly the same way through their own gates to switches 293, 29S and 297, respectively, whose other sides are connected to line L109. Pin 3 is associated with level B; pin 4, Wit}l level C; and pin 5, with level D.
~o stop the elevator on level A, for example, MPU 11 causes pin 2 of pluy Pl to go High and pins 3-5 to remain Low~ As the elevator approaches level D it closes switch 297, con-necting pin 5 of p].ug Pl and line L109 but nothin~ occurs 1 :

, 3 1g since pin 5 is Low. That is, the closure of switch 297 causes no change in the potential measured on line L109.
Likewise, as the elevator approaches level C it closes switch 295, again with no result. But as switch 291 finally closes it brings line L109 High since pin 2 of plug Pl is High. This High on line L109 is sensed by a buffer gate 299 and supplied on a line Llll to a ~ND
gate G31 (Fig. 35). Gate G31 is part of a triac gating circuit 3~1 identical to gating circuits 273, etc. The High on line Llll causes the output of gate G31 to go Low, providing in the same manner described above a gating signal for a triac 303. Triac 303 is connected at one main terminal to side LV2 of the power line and at the other main terminal to a vertical StQp solenoid 305 which when energized stops the elevator by, for ex-ample, causing a mechanical stop to be held in its path as shown in Canadian Patent No. 1,099,238. One side of vertical stop solenoid 305 i5 connected to side LVl of the power line.
Solenoid 305 is also connected to side ~V2 of the power line through a second triac 307 which is used to stop the elevator during reset of control circuit 7. During a systeTn reset the microprocessor causes pin 7 of plug P2 (Fig. 36) to be High. This High is sensed by a noninverting gate 309 and supplied on a line ~113 to a first input of a NAND gate G33. The High on pin 7 of plug P2 is also sensed by a noninverting gate 311 and supplied to the clock input of a number 4013, D-type latch 313. The Q output of latch 313 thereupon goes High. This High is sup-plied on a line L115 through a buffer gate 315 (Fig.
35) to the second input of gate ~33. The output of ga~e G33 is connected to one side of a transformer 317, the other side of which is connectecl to ~he gate terminal of triac 307. When the output of gate G33 goes Low, triac 307 is gated by current from trans-former 317 and vertical stop solenoid 305 is energized.
When the elevator stops at the desired lev-el, vending proceeds substantially as described in Canadian Patent No. 1,099,238. Specifically a tray or vend motor, not shown, goes through approximately one-hal of a cycle to convey the selected item 3 onto the elevator and then stops (this is called the 18n position of the tray motor). When the tray motor reaches the 180 position, it energizes a relay, designated N
herein and in the '238 patent, which causes the elevator motor to reverse and move the elevator back down to delivery station 105. After relay N is energized the operation of the present elevator control circuit is somewhat different from that disclosed in the '901 appli-cation.
In order for the elevator to freely return to delivery station 105 after the item has been con-veyed onto it, it is necessary that vertical stopsolenoid 305 not be energized. It will not be energized by triac 3G3 because MPU 11 causes pins 2-5 of plug Pl (Fig. 34) to go Low when the elevator stops. The energization of relay N (Fig. 36~ by the means disclosed in the l238 patent indicated ~3~9~9 by a box 317, when the tray motor reaches its 180 position causes two LEDs desi~nated by the reference numerals 319 and 321 to light. The light from the LEDs causes .a photo- -' transistor Q33 to conduct. Phototransistor Q33 is an NPN
t,ype transistor connected in the common-emitter configura~
tion so its collector voltage goes Low upon the lighting of LEDs 319 and 321. This Low is inverted by an inverter 323 and the resulting High is supplied to the reset inpu~
of D-type latch 313. The output of latch 313 goes Lo~, therefore, causing the output of ~ND gate G33 (Fig. 35) to be High. As a result no gating current can flow ~hrough transEormer 317, so triac 307 cannot energize solenoid 305 either. The ~ligh from inverter 323 is also supplied through ~ noninverting gate 325 to pin ~2 of plug Pl. Tnis high ' is a vendor status input signal to ~PU 11 -that the tray motor is in its 180 position.
It should be noted that although microprocessor 11, memory 9 and display circuit 15 are shown in block diagram form outside vendor 1 in Fig. 1 in actual fact all three ar~
contained inside vendor 1 and in particular ~ehind a front panel 327. Front panel 327 is secured,to a ri~ht-side panel 329 (E'iy. 37) on which control circuit 7 is mounted. Side panel 329 can be rolled forwardly part of the way oui oE
vendor 1 to the position shown in Fig. 37, on two guideways 33] and 333, shown in phantom.
~lost of control circuit 7 is enclosed in a sase 335. But tlle parts of circuit 7 whish the ser-~iceman needs to be able to manipulate are located outside case 335. Free vend switch 199, for example! is mounted on top of case 335.
And displa~ 15b is mounted on the outside of case 335.

Switches 60-71, which constitute serviceman-operable means for setting the values of at leas-t some of the parameters stored in memory 9, are mounted in a price-setting module 337 detachably mounted in a holder 339.
Specifically price-setting module 337 constitutes customer-inaccessible price-setting means for setting the prices of items 3a-3x stored in memory 9. Module 337 is customer-inaccessible because only the serviceman can roll panels 327 and 329 out from their closed position with panel 329 i.nside vendor 1 and panel 327 substantially flush with the front of the vendor to their open position shown in Fig. 37. Normally side panel 329 is locked in place by rneans of ~ lock and handle combination 341 moun-ted in panel 327. Clearly panels 327 and 329 constitute service-man-operable means for providing access to price-setting module 337 when they are in their open position and for preventing access thereto when they are in their closed posltlon .
Price-setting module 337 i5 normally connected to control circuit 7 by means of a plug 343 attached thereto and a socket 34S connected to the rest of circuit 7 by wires not shown. Plug 343 is shown unplugged from socket 345 in Fig. 37 to emphasize the fact that price-setting module 337 is serviceman removable. That is, the service-man can have a single price-setting module 337 which he takes from vendor to vendor. Typically, however, price-setting module 337 is left in vendor 1 and plug 343 is left plugged into its socket 345.

~3L3G~919 :

A more detailed view of price-setting module 337 and holder 339 is had in Fig. 38. Special note should be taken of mode-setting switch g8 mounted behind holder 339 with its actuator protruding into the interior of the holder. When price-setting module 337 is in holder 339, it engages the actuator of mode-set-ting switch 98, which causes the blade of switch 98 to contact contact 98a (Fig.
17), which puts circuit 7 in the vending mode. That is, mode-setting circuit 93 is responsive to price-setting module 337 being in holder 339 to set control circuit 7 in its vending mode. When module 337 :is removed from the holder, it no longer engages the actuator of switch 98, so the blade oE switch 98 swi-tches to contact 98b, which sets control circuit 7 in -the price-setting mode. Since holder 339, module 337 and switch 98 are accessible only when panels 327 and 329 have been moved to their open posi-tion, mode-setting circuit 93 is operable to set control circuit 7 in the price-setting mode only when the service-man access means, i.e., panels 327 and 329, is open.
Price-setting module is about 2-1/2" x 4" x 1"
in size and is therefore of such a size that the service-man can hold it in one hand, leaving his other hand free to operate the module by pressing the desired keys. Module 337 has a flexible cord 347 secured at one end to its body and at the other end to plug 343, this cord being of sufficient length, when extended, to allow the serviceman to stand in front of panel 327 while changing prices.
The only parts of switches 60-68 and 70 showiny on module 337 are their respective actuator keys arrayed ~6 , -to form a numeric ke,yboard, indicated generally at 349.
Switch keys 69 and 71 are not part of keyboard 349.
An alternative embodiment of price-setting module 337 is shown in Fig. 3g and designated by the reference nu-meral 351. Price-setting module 351 has a five-position rocker switch 353 in place of numeric keyboard 349. Rocker switch 353 is shown in its middle, i.e., off, position in Fig. 39. Moving switch 353 one position toward the word ~
"UP" written on the module closes switch 73 (Fig~ 16), while moving it to the second position in that direction also closes switch 75. Moving switch 353 one position toward the word "DOWN" closes switch 74 ~Fig. 16), while moving it to the second DOWN position also closes swi~ch 75 again.
For the convenience o~ the serviceman, display 15a is included in price-setting module 351 rather than on the ,fron-t of vendor 1. Connection between module 351 and socket 345 is by a flexible cord 347a and a plug 343a, the plug having eleven additional pins to accommodate the display.
Another alternative embodiment of price-setting module 337 is a price-setting module 355 (Fig. 40) which has a dial 357 with prices indicated thereon. Module 355 includes a control knob 359 having a pointer 361 for indi -'~'' cating any one of the prices on the dial. A serviceman using module 355 selects prices by simply turning control knob 359 until pointer 361 points to the desired price. Module 355 is connected to socket 345 by a flexible cord 347b and a plug 343b. Each price printed on dial 357 has an associ-ated switch, not shown, the closure of which indicates to MPU 11 the corresponding price. Appendix A must be modified slightly to allow MPU 11 to decode such switch closures.

.

An alternative to the embodiment of this inven-tion shown in Figs. 37-40 is shot~n in Figs. 41 and 42.
Switches 60-71 in this embodiment are mounted in a drawer 363 which, when a lock 365 is unloc~ed by the serviceman, pivots outwardly and downwardly about the bottom of the drawer un~il stopped by two stops 367 and 369 which are part of the rear of drawer 363. Drawer 363, therefoxe, also constitutes serviceman access means for access to price-setting switches 60-71. Switch 98 in this embodiment is mounted directly behind drawer 363, positioned so that when the drawer is closed control cixcuit 7 is in the vend-ing mode and when drawer 363 is open circuit 7 is in the price-se~ting mode. Switch 98, therefore, also constitutes ~eans for ensuring that control circuit 7 is in its vendiny mode when the serviceman access means is closed.
The operation of control circuit 7 is as follows:
Microprocessor 11 performs its logic and arithmetic opera-tions in the order determined by its program tApp. A). It will, however, when a Low-to-High transition occurs at the RESET input (pin 40) read the data at a predetermined address, namely 2FFE and 2FFF, and start step-b~-step operation of the program from the location specified in that predetermined address, no matter where it had previously been in the pro-gram. Microprocessor 11 also stops, or interrupts, its per-formins of the program when a Low appears at its IRQ input(pin 4). Upon a Low on the IRQ input, MPU 11 automatically reads the address stored at 2FF8, 2FF9 and begins per-forming the program from that stored address. (Motorola 6800 microprocessors read the da-ta at FFFE, FFFF upon a , 9i~ -Low-to-High transition at the RESET input and read the data at FFF8 and FFF9 upon a Low at the IRQ input. These addresses correspond to the above addresses in the current system.
A Low-to-High transition appears on the RESET input of MPU 11 during power on. It is supplied from clock 17 through connector PE and line L67 to the RESET input. MPU 11 then looks to address 83FE, 83FF and reads the address, 2000, stored there, which is the address of the power-on subroutine BOOT in the program. The first action MPU 11 takes in sub-routine BOOT is to set the noninterrupt mask of MPU 11 to avoid interrupts on the-uninitialized system. Then it clears memory locations 0030 0076 in chip RAMl. These locations are used as a temporary storaye, i.e., a scratchpad, ~or the values of several variables which MPU 11 uses in executing the program. The most important of these variables and their functions are explained below.
FLG5 is an eight bit status flag, each bit of which signif1es a particular status when High. If FLG5 = 01, i.e., bo is High, it means that the CREM has been disabled. FLG5 =
02 means that the number to be displayed in displays l5a or 15b have a leading zero. FLG5 = 04 signifies a full escrow payback. FLG - 08 indicates long delay needed. FLG5 = 10 tells the ~PU to display the next digit on displays 15a and 15b. FLG5 = 20 tells MPU 11 to make change using the least number of coins. FLG5 = 40 signals the MPU to display two most significant digits, and FLG5 = 80 tells microprocessor 11 to load a price. ~ny number of bits may be set at any given instant. For instance, if leading zeroes are present and the CREM has been disabled, the value of FLG5 is 03.

~13(~19 FI.G6 and FLG7 are sta-tus fla~s used to control the elevator and the payback operation of vendor 1.
TBC is a buffer for -time-base-clock 113. SPEED
1 is a buffer for timer or speed-sensor clock 107, which - 5 senses the speed of the elevator motor.
COIREG is a buffer for storing information con-cerning the detection of a coin or bill upon deposit thereof in vendor 1 by the customer. INV04 is where the total accumulated sales figuré is stored in chip ~1. CREDH
is where the customer's total credit is stored. The number of coins and bills of a particular kind deposited by the cucton;er are stored in FENIC (nickels~, FEDI (dimes" FEQUAR
(quarters), FEONEC (dollar coins), FEONEB (dolla~,^ bills), and FETWO (two-dollar bills) for use in returning to the customer the exact kinds and number of coins and currency he deposited, i~e.~ a full-escrow payback.
COSTH is where the cost of the selected item is stored. CONTYP is used as a buffer in determining the type of coin/currency deposited and to be returned.
The column information of a selection is stored in the buf~er HORSOL while the row inormation is stored in the buffer SELECT. Price information from switches 60-71 is stored in KEYBDl and KEYBD2. The PRICE variable, which starts at address 0084, is not used in this embodiment of the invention. ~ , The first forty-ei~ht bytes of chip RAMl, 0000-002F, are used for the stack o MPU 11. Of course, the rela-tive positions of the stack and the scratchpad could be , ~130~ ~

reversed, but it would have the disadvantage that under abnormal conditions the stack could push data down into the scratchpad, thereby altering information stored there.
With the present circuit on the other hand~ abnormal con~
ditions lead the vendor into a reset condltion and restore normal operation for the next vend. ~ -Next, the input/output~I/O)of the system is con-figured by MPU 11. That isl PIAs PIAl-PIA6 are con~igured to act as inputs and outputs as required. As is explained in "M6800 Microcomputer System Design Data" (Motorola, 1976) each PIA has two Output InterEace Registers ~or Peripheral Registers) normally called the A and B registers, two Data Direction Registers (one for each Output Interface Register) and two Control Registers (one for each Output Inter~ace Register)~ In the program the ~ata Direction Reyister for the "A" Output Interfa'ce Regi'stex and that Interface Register itself are indicated by the PIA number with the suffix AD, while the "B" Data Direction Registex and the "B" Output Interace Register are indicated by the PIA number and the sufEix BD. For example, the Data Direction Register for the A side oE chip PIA2 is indicated by the symbol PIA2AD
and the symbol for the B side Data Direction Register is PIA~BD. The Control Registers are identiFied similarly, except the suffixes are AC and BC. Hereina~ter in the specification the Data Direction Register will be dis-tinguished from the Output Interface Register by designating the latter by its PIA number and the suffix ~ or B only.
The Output Interface Registers each have eight peripheral data lines associated wi-th them. The peripheral data lines associated with the "A" Ou-tput InterFace Registers have the standard designation PA0-PA7 while those Eor the "B" Registers have the standard designation PB0-PB7.

The Data Direction Registers determine whether the corresponding peripheral data line of the Output Inter-ace Registers are inputs or outputs. For example, in con-figuring the I/O of the system, MPU 11 stores 3F, i.e., 0011 1111, in PIA2AD and PI~2BD. This makes peripheral data lines PAO-PA5 and PBO-PB5 of PIA2A and PIA2B outputs and pe-ripheral data lines PA6-PA7 and PB6-PB7 inputs. In terms of pin members of plug Pl (Fig. 12), pins 2-7 and 35-40 are out-puts of pins 8-9 and 41-42 are inputs. A quick examination of the pins and their connections reveal that this is the proper configuration. Pins 2-5 (Fig. 34), pin 6 tFig. 33) pin 7 (Fig. 31), and pins 35-40 (Fig. 35) o~ plug Pl are indeed outputs, and pins 8 and 9 (Fig. 32), pin 41 (Fig~ 16) and pin 42 (Fig. 36) are inputs.
MPU 11 addresses the I~Al~' side of each PIA by 5Up-plying a Low on address line Al, which is connected to pin 35 of all the PIAs. A High on line Al, on the other hand, addresses the 'IB'' side of the particular PIA selected.
When a peripheral data line is programmed as an output~ the signal supplied on the corresponding data line from ~U 11 to the PIA appears directly on that peripheral data line. Conversely, i~ a peripheral data line is pro-grammed as an input, the signal level present on that per-ipheral data line appears directl~ on the corresponding data line or MPU 11 during a read operation. Using the above example, peripheral data line PA2 of PIA2A has been progra~med as an output~ If MPU 11 then supplies a H1gh on data line D2 to PIA2A, specifically to the D2 pin (pin 31) ' 1~3~9~

of chip PIA~, peripheral data line D2 of PIA2A goes Hlgh Peripheral data line PA7 of PIA2A is an inpu-t. If the signal level present at PA7 is a Low, for example, during the time MPU 11 reads PIA2A, the Low will appear on data line D7 of the MPU, by way of pin 26 (the D7 pin) of chip PIA2 and line D7a.
After initializing the Data Direction Registers, the microprocessor initializes the Control Registers -to enable some interrupts. Each PIA has two interrupt input lines for its "A" register, indicated by the reference characters CAl (pin 40 of the PIA) and CA2 (pin 39), as well as two such lines for its "B" side, viz., CBl ~pin 18) and CB2 (pin 19). Inputs on the CAl and CA2 input lines can cause an "A" register interrupt output, indicated IRQA
(pin 38) to go Low. ~ikewise inputs on the CBl and CB2 interrupt input lines can cause an IRQB (pin 37 of that PIA~
interrupt output to go Low. The specific voltage levels necessary to cause these IRQ outputs to go Low are determined by the contents of the Control Registers associated with the particular PIA and are explained in the above-mentioned Motorola publication. The IRQA and IRQB outputs of all the PIAs are directly connected to the IRQ input (pin 4) of ~PU 11 by a line L117. A Low on line L117 caused by any one of the PIAs will appear at the IRQ input of MPU 11 and cause it to commence its interrupt sequence.
As an example of enabling interrupts, in subroutine BOOT 72 the microprocessor loads the value 07 into PIA2BC, PIA3BC, PIA5BC and PIAlAC. As a result the IRQB output ` - - ` 3~fi3 ~:13C~

(pin 37) of chip PIA2 will cJo Low whenever its CBl input (pin 18) goes High. ~sincJ the "A" register of chip PIAl as another ex~lmple, its IRQA output (pin 38) will go Low whenever its CAl input (pin 40) goes l~ish.
The CAl input of chip PIAl is connected throu~h pin 9 of plug P2 to the output of nickel indicator circuit 129 (Fig. 23). When a nickel is deposited in vendor 1, the output of circuit 129, and therefore the CAl input of PIAlA (Fig. 6), goes High generating an interrupt si~nal on line L117. Likewise the CBl input of chip PXA5 (Fig. 14) is connected through pin 38 o~ plu~ P2 to -the output of ~ime indicator ~ircult 131 ~L~ . 23), the C~l input of chip PI~3 (Fig. 12) is connected throuyh pin 20 of pluc~ Pl to the output of quarter indicator circuit 133 (Fig. 23), and the CBl input of chip PIA2 (Fig. 12~ is connected through pin 25 oE plug Pl to the output of dollar coin indicator ~' circuit 135 (Fig. 23). Whenever a coin is deposited into vendor 1, one of these PIAs will generate an interrupt signal.
After initlalizing the coin interrupts, MPU 11 checks the status of vendor 1. Specifically, in subroutine M~CSTA ~PU 11 determines if the elevator is at delivery station 105. It does thls by testing line PB4 of chip PIA5 (pin 14) which is connected through pin 10 of plug P2 to the output of gate 235 of interlocking circuit 227 (Fig. 32). Line PB4 will he High if the elevator is in fact at delivery station 105, since only then is the blade of elevator location switch 229 (Fi~. 32) in contact with contact 229a. If the elevator is no-t at the delivery 5~

sta~ion, MPU 11 tests line PB7 chip ~IA2 (in s~lbroutine TM180D) to determine if the tray motor is at the 180 off home position. Line PB7 (Fig. 12) is connected throu~h pin 42 of plug Pl to the output of gate 325 IFig. 36).
This output, as explained above, is Hi~h when down relay N
is energized, which occurs while the tray motor is in its 1~0 position and the elevator is up at one of the levels or headed back down to the delivery station. If the tray motor is in fact at the 180 position, MPU 11 supplies a High to line PA4 of chip PIA2 (Fig. 12). This High is sup-plied through pin 6 of plug Pl to run relay circuit 241 (Fig. 33) where it causes relay solenoid 2~5 to he ener-yized, thereby causin~ the elevator to move down to delivery station 105.
Once the elevator reaches the delivery station, MPU 11 jumps to subroutine RDTOSL where it retrieves accumu-lated total sales information from chip EAROMl. The micro-processor supplies the address of the total accumulated sales figure, i.e., lD, to PIAlA (Fig. 6). This causes pins 2 and 4-6 of chip PIAl to go High and pin 3 to go Low.
Pins 2-6 of chip PIAl are connected to the address lines (pins 19-23) of chip EAROMl (Fi~. 7) by lines A0f A4f, so these slgnals from chip PIA1 address word lD in chip EAROMl.
MæU 11 also causes pins 8 and 9 of chip PIAl to go High and pin 7 to be Low. The ~Iigh on pin 9 is supplied on a line L119 to a NAND gate G35 (Fig. 8), the other input of which is normally High. The resulting Low output of gate G35 is inverted by an inverter 365 and supplied on a line L121 to pin 27, the chip select input, oF chip EAROMl, 9~ :

thereby selecting it. The High on pin 8 and the Low on pin 7 of chip PIAl (Fig. 6) are supplied to pins 25 and 26 respectively of chip EA~OMl ~Fig. 7). Pins 25 and 26 of chip EAROMl are mode control inputs. A High on pin 25 and a Low on pin 26 put chip EAROMl in the read mode.
Before MPU 11 can read the inEormation stored at address lD in chip EAROMl, however, it must cloclc the EAROM.
This is done through PIAlB (Fig. 6). Pin 19 of chip PIAl the CB2 pin, is connected to the clock input (pin 18) of chip EAROMl (Fiy. 7). MPU 11 programs the CB2 pin to be an output and causes its signal level to go High and -then back Low. This clocks chip EAROMl and, after a required access time, MPU 11 reads the data stored in chip EAROMl at address lD.
MPU 11 reads the eight most significant bits~of the data stored at lD in chip EAROMl through chip PIA6 (Fig. 6). These eight most significant bits are supplied from data pins D8-D15 (pins 9 16) of chip EAROMl via lines L51, L53... , L65 to the PB0-PB7 peripheral data lines (pins 10-17) of chip PIA6 (Fig. 6) where they can be read-by MPU 11. MPU 11 stores these bits in the buffer COSTH. The eight least significant bits of the data are supplied from data pins D0-D7 (pins 28, 1-6, and 8) of chip EAROMl via lines L35, L37, ... , L49 to tne PB0-PB7 peripheral data lines (pins 10-17) of chip PIAl (Fig. 6~. The MPU stores these bits in buffer COSTH~l, and stores the contents of COST~ l and COSTH in INVO4+1 and INVO4. In the same way, .:

MPU 11 then reads the data stored at address lE in chip E~RO~Il and st~res this in locations INVO4+2 and I~VO4+3.
Of course, it is not absolutely necessary that the t~tal ¦~
sales figure be stored in chip ~11 and be upAated there.
It is also directly updated in chip E~RO~l. It could be preferable to upda-te the total accumulated sales figure in chip RAMl, however, and to store it in chip EARO~
only upon the occurrence o a power loss or the like be-cause the EAROMs have a relatively small upper limit on the number of times that data may be written in each address. Updating the total accumu~ated sales figure in the EAROMs after every sale might in som~ applications fatigue the EARO~ .
After obtaining the total sales figure from chip EAROMl, MæU 11 energizes solenoid 223 (Fig. 31) to unlatch door 117. Solenoid 223 is energized by MPU 11 supplying a High on data line DS to pin 28 of chip PI~2 while selec-ting the "A" side of the PIA, which causes the corresponding pe-ripheral data line, P5A, to go High (Fig. 12)~ P5A (pin 7 of chip PIA2) is connected through pin 7 o plug Pl to door lock relay circui-t 221 (Fig. 31~. The High on plug Pl, pin 7 turns on transistor Q29, thereby energizing relay 223 which through its contacts energize the lock solenoid.
Next, klPU 11 initializes a credit recall inter~
rupt by loading the data 07 into PIA6BC (Fig. 6). Tnis ensures that if the CBl input o chip PIA6 ~oes ~igh, chip PIA6 will cause its IRQB pin to go Low, ~Jhich Low will be suppliel on line L117 to MPU 11 to cause it to commence an interrupt sequence. The CBl input ~pin 18) of chip PIA6 is connected through pin 20 of plug P2 to the output of gate 181 in credit recall circuit 179 ~Fig. 27), which output will be ~lig}l if the customer presses the coin return switch.
~ IPU 11 also initializes payout request and clear total sales interrupts at this -time by loading 07 into PIA6AC and PIAlBC. The CAl input of chip PIA6 (Fig.
6) is connected through pin 1 of plug Pl to the output of inverter 191 in circuit 179 (Fig. 27). This output yoes ~liyh, thereby generating an interrupt, if the service-man presses one of the four switches for empt~ing the coin tubes. The CBl input of chip PI~l (Eig. 6) is connected through pin 1 of plug P2 to the output of gate 215 (Fig. 30). As explained above, the output of gate 215 goes High when the serviceman closes switch 213 to re-set the total accumulated sales figure. This High output, because of the initialization of PTAlB, generates an inter-rupt.
Sèlection and price interrupts are next initial-ized by MPU 11 loading lF into PIA4BC ~Fig. 13). If either the CBl or CB2 input of chip PIA4 goes High after this initialization, chip PIA4 will make its IRQB pin go Low, which will initiate an interrup-t sequence in ~IPU 11. The CBl input of chip PIA4 is connected through pin 35 of plug P2 to the output of gate G21 in mode setting circuit 93 (Fig. 17). The CB2 input is connected through pin 50 of plug P2 to the output of gate G23 in mode-setting circuit 93.

~3~gi~

After initializing these interrupts, MPU 11 initializes dollar coin escrow circuit 173 (Fig. 25).
The dollar coin escrow solenoid is not normally energized, and the initialization of circuit 173 ensures that this is the case. MPU 11 supplies the data 04 to PIA6A (Fig.
6) which makes peripheral data line PA2 (pin 4) of that PIA
High. Data line PA2 of chip PIA6 is connected through pin 43 of plug Pl to escrow circuit 173 (Fig. 25). The High on plug Pl, pin 43 ensures that line L89 is also High, which prevents energization of the dollar coin escrow solenoid. A Low on that pin, however, will result in energization o~ the escrow relay and the escrowing of dollar coins.
After initializing the dollar coin escrow circuit, MPU 11 sets product sensing circuit (product sensor) 99 (Fig. 18) for operation. Specifically, MPU 11 supplies the data 40 to PIA5BD. This causes data line PB6 of chip PIA5 (Fig. 14) to be High. Line PB6 (pin 16) is connected through pin 12 of plug P2 to a noninverting gate 367, the output of which is connected to the base of P~P transistor Q35 (Fig. 18), connected in the common collector configura-tion. LEDs 101 and 103 are connected on one side to the emitter of transistor Q35 and on the other to a ~12V source.
The High on pin 12 of plug P2 removes bias from the base-emitter junction of transistor Q35. As a result LEDs 101 and 103 do not light. That is, the normal state of LEDs 101 and 103 is o~f. They will be turned on as required to sense items 3 at delivery station 105.

-~3~

Next, MPU 11 reads the data from all the PIA
Output Interface Registers in subroutine CLRINT. This ' c~ears any interrupts which may be present. During power-up, undesired interrupts are sometimes generated. Clear-ing these interrupts durlng the power-on sequence prevents these erroneous interrupts from causing a malfunction of control circuit 7.
The next step of the power-up subroutine is to pulse validator bill acceptor circuit 195 (Fig. 28) to ensure that the validator is in a known condition after power-up.
MPU 11 accomplishes this by supplying 08 to PIA6A, causing peripheral data line PA3 of chip PIA6 (Fig. 6) to go E~igh.
~his line (pin 5 of the PIA) is connected through pin 45 of plug Pl to circuit 195. The ~Iigh ou-tput on line PA3 cau~es transistor Q23 to conduct, drawing line L105 Low, as is re-quired to cause the validator to accept a bill. After a delay, MPU 11 causes line PA3 of chip PIA6 to go Low, which removes the Low from line L105.
Finally MPU 11 clears its non-interr~lpt mask and exits to standby routine or loop (FIRTSl) where it awaits interrupts. Control circuit 7 is now operational, ready to perform its various functions.
One function of control circuit 7 is to control a vend operation. Suppose a customer approaches vendor 1 and decides to purchase item 3i which costs $1.55, i.e.j the price s~ored in chip EAROMl for item 3i is $1.55. The customer first deposits a dollar coin in coin slot 5. The coin changer immediately sends a pulse to dollar coin indi-cator circuit 135 (Fig. 23).- This pulse appears as a spike ~3~

on pin 25 of plug Pl ~hich is connected to the CBl input ~pin 18) of chip PIA2 (Fig. 12). As the CBl input goes E~igh, the IRQB output of chip PI~2 ~oes Low, supplying an interrupt signal on line L117 to the IEZQ input (pin 4) o~ ~IPU 11. In response, the microprocessor jumps to loca-tion 83F8 and reads the address stored there, which is 27AD.
MPU 11 tnen proceeds to execute the program from step 27~D,~
~hich is subroutine INTERP.
When MPU 11 receives an interrupt on line L117, it does not know which PIA generated it. Consequently, it must check, or poll, the vari.ous PIAs to determine which interrupt has been generated before it knows what action to take. First MPU 1l clears the carry bit, then it checks to see if time-base clock 113 (Fig. 20) caused the inter-rupt. MPU 11 then determines whether elevator speed sensor circuit 106 (Fig. 19), i.e., speed-sensor-clock 107, caused it. These steps are described in detail below in the dis-cussion of the function of eleva~or control.
Next, microprocessor 11 checks or coin or cur rency interrupts. MPU 11 reads PIA3A (Fig. 12) whose PA3-PA7 peripheral data lines are connected through pins 30-34 of plug Pl to -the outputs of dollar bill indica-tor circuit 123 (Fig. 22~, dollar coin indicator circuit 135 (Fi~. 23), quarter indicator circuit 133, dime indicator circuit 131 and nickel indicator circuit 129 respectively. Because it is a dollar coin that has been deposited, line PA4 will be High and MPU 11 will read 0001 0000 ~binary). This in~orma-tion is temporarily stored in one of MPU ll's two accumu-lators.

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MPU 11 then checks, in subroutine COI05, to see if a dollar coin has been deposited b~ e~aminin~ bit 7 of PIA2BC (Fi~. 12). When the dollar coin was detect~d, -the outpu-t of gate 14~ in dollar coin indicator circuit 135 (Fig. 23) went Hi~h. This ~liyh was supplied through pin 25 of plug Pl to the CBl input of chip PIA2, setting bit 7 of control register PIA2BC High. Since this bit is - Hi~h, a dollar coin caused the interrupt. Once this has been determined, Mæu 11 disables the dollar coin interrupt 1~ by storing the data 04 in PIA2BC. It then clears the inter-rupt by reading PIA2B.
The output of PI~3A, i.e., 0001 0~00 (binary~ is th~n temporarily stored in the buffer COIREG. Note that since different coins or bills will cause diE~erent bits of PIA3~ to be ~Iigh, the contents of COIREG will uniquel~-represent the type coin/currency deposited in ~endor 1.
~fter the coin information is stored in COIREG, MPU 11 initializes an anti-}ackpot delay (AJD) corresponding to a dollar coin. Each type coin has its own A~D which is used 2~ to keep the interrupt for that coin disabled during its passage through the coin sensor in the coin handler. This prevents coins with the center drilled out, i.e., washer-shaped coins, from interrupting twice and thus being credited twice. Of course, the transit time through the sensor will depend upon the sensor's beam width, the diameter of the coin, the inclination of the coin channel, the coefficient of friction between the coin and the channel and other sim-ilar factors. As a result the anti-jackpot delay for each coin is likely to differ depending upon the particular make .

or model of coin handler in vendor 1. For this partlcular coin handler the AJD for dollar COills is 70 milliseconds;
for quarters, 40 ms; for dimes 70 ms; and for nickels 30 ms.
Of course, new values should be obtained for the AJDs, in light of the above factors, when using control circuit 7 with any other coin handler.
MPU 11, after set*ing the AJD for the dollar coin, enables interrupts from time-base-clock 113, in subroutine VENDOB, by loading the data 07 into PIA4AC (Fig. 13). This ensures that when input CAl of PIA4A goes ~ligh, an interrupt will be generated. The CAl input oE PIA4A is connected thro~gh pin 36 o plug P~ to ti~e-base-clock 113 (Fig. ~0).
Whenevex clock 113 generates a pulse, which is every ten ms., MPU 11 will be interrupted. MPU 11 uses these time-base-clock interrupts to measure the anti~jackpot delay of the coins.
After enabling the time base-clock interrupt, MPU 11 clears all present in~erxupts, in subroutine CLRINT
as described above, and jumps to subroutine CONTSK where the customer's credit is developed. In CONTSK, ~U 11, aftex identifying the coin as a dollar, erases COIREG, and energizes the ~l-coin escrow relay by storing the data "00"
in PIA6A (Fig. 6). This causes peripheral data line PA2 o chip PIA6, which is connected through pin 43 of plug Pl to $1-coin escrow relay circuit 173 (Fig. 25) to go LO~J.
As a result line L89 of circuit 173 provides a ground path for the dollar coin escrow relay, causing it to be ener-gized and thereby trapping the dollar coin in the escrow position in the coin handler.

~3~-lg The customer's credit, stored in buffers CREDH+2 and CRED~3, is updated by MPU 11 to reflect the deposit of the dolla~ coin. Specifically MPU 11 s-tores 01 in CREDH-~2 and 00 in CREDH+3. This is a binar~-coded decimal (BCD) representation of the customer's credit. In other words, MPU 11 is responsive to. the interrupt signal from . PI~2B, which is an input thereto indicating the deposit of money, i.e., a dollar coin, to determine the amount of credit accumulated as a result of that deposit.
Microprocessor 11 next tests whether the number of dollar coins deposited by the customer is greater than twenty. MPU 11 does this ~Gr all types of coins to limit scavenging. Control ci.rcuit 7 returns exactly the same number of each type of coin that the customer has de~osited upon the closing of a coin return switch CR. A customer~
wishing to take advantage of this feature could insert, e.g., fifty dimes into vendor 1, and receive the bottom fifty coins in the dime change tube upon pressing coin return switch CR.
C].early such a customer could readily empty the coin change tubes. To prohibit`this, control circuit 7, as mentioned above, tests the contents of the speci~ic number-of-coin buffers, e.g., FEDI, everytime a coin of that type is in-serted into vendor 1. If the number of coins of that type exceeds twenty, MPU 11 disables the CREM and returns the customer's credit in the same coin types as was entered.
The CREM is disabled by MPU Il supplying a signal through PIA3B to CREM control circuit 177 (Fig. 26). As the program is written, MPU 11 also disables the CREM whenever -the cus-tomer's accumulated credit is over $4.95. The return of the cus-tomer's credit is discussed below. : .
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In our example where the customer has deposited only one dollar coin, the CRE~I is not disabled and ~IPU 11 stores the fact that a dollar coin has been inserted by storing the data 01 in dollar-coin buffer FEONEC.
As mentioned above, during the anti jackpot delay for the dollar coin, the time-base-clock 113 (Fig. 20) inter-rupts every 10 ms. After seven of these interrupts, MPU 11 determines through subroutine TCB01 that the AJD for the dol-lar coin has ~xpired, so it reenables the dollar coin inter-rupt. Enabling of the dollar coin interrupt is accomplished by s-toring the data 07 in PIA2BC ~E'ig. 12). By thus setting the first two bi-ts of PIA2BC ~ligh, MPU 1' ensures that a llicJIt on input CBl of chip PIA2 will generate an interrupt.
As explained above, this input will go High only when dollar - 15 COill indicator circuit 135 (Fig. 23) indicates the deposit of another dollar coin.
It should be noted that the customer's credit is stored in the number of coin buffers, e.g., PEONEC, and in credit buffers CREDH+2 and CREDH~3. The number of coin buf-fers and the credi~ buffers have diferent functions, ho~-ever. The number of coin buffers are used to return coins in full-escrow while the credit buffers are used to allow purchase of an item 3. These buffers are independent, and incorrect data contained in one does not prevent the other fro~ functioning correctly.
After enabling the dollar coin interrupt and stor-ing the cuStQmer's credit as outlined above, ~U 11 returns to standby loop FXRTSI, which includes the display subroutine DISPLY. Xn subroutine DISPLY, MPU 11 de-termines if control .

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~3~9 ~ 9 circuit 7 is in the vendin~ mode or the price-setting mode by testing PIA5B. Peripheral data line PBl of chip PIA5 tFig. 14) is connected throu~h pi.n 23 of plug ~2 to the output of gate 97 in mode-settin~ circuit 93 (Fig. 17).
- 5 When control circuit 7 is in the vendin~ mode the output of gate 97 is ~ow. MPU 11 is responsive to the resulting Low on line PB1 of chip PIA5 to branch to DISP72 which starts a credit/total sales display subroutine.
In the credit/total sales subroutine, MPU 11 se-quentially displa~s the digits of the total accumulated sales figure and then the diyits of accumulated c:redit as follows: Di.splay 1.~6 has ~.ix seven-sec3men~. displ.ay d.i~its or units arran~ed in ~ linear array which are used to dis-play the total accumulaked sales figure. (The most sig-nificant digit, i.e., MSD, of that.display is shown at the bottom of display 15b on Fig. 15 while the least signifi-.
cant digit, i.e., LSD, of that display is shown at the top Therefore, display 15b can display six digits of a total accumulated sales figure. These six digits are stored in BCD form in total sales inventory buEfers INV04-~1, INV04+2 and INV04+3, the two MSDs being stored in INV04+1. Sup-pose that the total accumulated sales figure before our hypo-thetical customer approached vendor 1 was $10.95. In that case the contents o-f INV04+1 = 0000 0000 (binary), the contents of INV04~2 - 0001 0000 tbinaxy), and the con tents of INV04+3 - 1001 0101 (binary). MPU 11 reads the contents of INV04-~1 and stores this in.one accumulator.
It then tests the highest four bits, corresponding to the value that should appear in the MSD of displ~y 15b, -to , .6G :

determine if that value is a zero. It is, so it masks the MSD of display 15b. Masking of any digit of displays 15a and 15b is accomplished ~y supplying ls to pins 27-30 o~
plug P2, while selecting the digit for display. Pins 27~
30 of plug P2 are directly connec-ted to the BCD input pins of decoder 47. The output of decoder 47 is supplied to driving transistors Q2-Q8 which drive the segments of whichever digit in the displays is selected at that time.
Selection of a digit is accomplished by causing the output of one of inverters 49-58 to go Low. Each inverter is con-nected to a single digit of the displays, so the Low out-pu~ of that invert~r, while the ou-tputs o the ot!lers are High, causes its digit to be energized, displaying the numeral corresponding to the signals supplied from decoder 47 at that time. When the signals at all the BCD inputs of decoder 47 are High, however, the output of the decoder is such that none of the segments in the selected digit are lit. For example, to mask the MSD of display 15b as required, MPU 11 stores the data "4F" in PIA5A. This causes peripheral data lines PA0-PA3 of chip PIA5 (Fig. 14j to be High. These Highs are supplied o~er pins 27-30 of plug P2 to decoder 47 (Fig. 15), resulting in a masking output thereof.
Line PA6 of chip PIA5 is also High. This High is supplied through pin 33 of plug P2 to inverter 58. The resulting Low selects the MSD of display 15b but since the BCD inputs to decoder 47 are all ls no numeral is displayed.

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MPU 11 then tests the lo~est Eour digits of buffer INV04-~1 which contain the value of the second MSD
of displays 15b. These are also zero, so ~IPU 11 masks that digit by supplying the data 8F to PIA5A. This again causes lines PAO-PA3 of chip PIAS to go High, masking any - selected digit. Line PA7 is a~so High at this time. Line PA7 is connected through pin 34 of plug P2 to inverter 57 (Fig. 15), whose output is connected to the second MSD, i.e., the second digit from the hottom, of display 15b.
The second MSD is, therefore, selected and masked by MPU 11.
Next, MPU 11 tests the contents of the hi~hest our bits of buf~er INV04-~2. Since khe valu~. o thqse bits is not zero, but rather 1, MPU 11 does not mask the next digit. Nor, once i~ has detec-ted a non-zero digit on a display will it mask lower zero digits. MPU 11 then causes display 15b to display the numeral "1" in its third ~lSD, i.e., that digit third from the bottom of the display, by storing the data 01 in PIA5A and the data 80 in PIA4A.
This causes peripheral data line PA0 to be ~igh and lines PAl-PA3 to be Low. Decoder 47 is ~esponsive to this par-ticular set o~ signal levels to send out signals to light the numeral "1" on the selected digit. Supplying the data ~- ;
80 to chip PIA4 causes its PA0-PA6 lines to be Low and its PA7 line to be High. The PA7 line of chip PIA4 is connected through pin 5 of plug P2 to gate 84 ~Fig. 16), which is connected by a line L123 to inverter 56. Inverter 56 is connected to the third MSD of display 15b, so when its output goes Low, that digit will display the numeral "1", which is the most sig~ificant non-zero digit of the total -accumulated sales figure. Ho~ever, as mentioned above, inverter 56, along with inverters 53-55 and 57-58, is normally disabled, so although ~lPU 11 continuously sup-plies -the total accumulated sales data to display 15h~
this display is not activated until the serviceman uses his key 203 (Fig. 30).
MPU 11 then supplies the data 00 to PIA5A and the data 40 to PIA4A. Peripheral data line PA6 of chip PIA4 is therefore the only High line of PIA4A, while the output of decoder 47, controlled as above by the output of lines PA0-PA3 of chip PIA5, corresponds to the display-iny of the numeral "0". Line PA6 of chip PI~4 is con-nected through pin 4 o~ plug P2 -to ~ate 83 which is in turn connected by a line L125 to inver-ter 55. If in-verter 55 were enabled, therefore, display 15b would at this time display the numeral "0" in the thir~ digit from the top.
In exac-tly the same manner, MPU 11 then supplies display 15b with the numeral "9" in the second digit from 2~ the top of the display This digit is selected by the data 20 being stored in PIA4AD, causing :line PA5 o~ chip PIA4 to be High while the other peripheral data lines are Low. Line PA5 is connec-ted through pin 3 of plug P2 to gate 82 (Fig. 16), which is connec~ed ~hroug~ a line L127 to inverter 5~. MPU 11 then supplies the numeral "5"
to the top digit in display 15b. That digit is selected ~y storing the data 10 in PIA4A. Line PA4 of chip PIA4 goes High and through pin 2 of plug P2 supplies that High to gate Sl (Fig. 16~. Gate 81 is connected through , ' 91~

a line L129 to inverter 53, which is connected to the top digit, i.e., the LSD of display 15b. When enabled by key 203, display 15b displays 10.95, the ~otal accumulated sales figure. Of cours~, because ~U 11 perÆorms this step very rapidly, it appears to the naked eye that all the digits are lit at the same time.
Ater displaying, or attempting to display, the : :
total accumulated sales figure, MPU 11 causes the customerls credit to be displayed. Display 15a, like display 15b, has its MSD at the bottom on Fig. 15. The two LSDs of display 15a are at the top of the display. The digits of display lSa ar~ sele~ted b~ i~U 11 c~using peri~her~l data lines PAO-PA3 of chip PIA4 to be High. A High on line PA3 is supp]ied through pin 17 oE plug P2 to gate 80, a ~ligh on line PA2 is supplied through pin 16 of plug P2 to gate 79, a High on line PA1 is supplied through pin 15 of plug P2 to gate 78, and a High on line PAO is sup-plied through pin 14 of plug P2 to gate 77. Gates 77-80 are connected by four lines L137, L135, L133 and L131 to inverters 49-52.
Display of the customer's credit, therefore, pro-ceeds as follows: MPU 11 first examines the four highest bits of the contents of buffer CREDH+2. As the reader will recall, the contents of buffer CREDH+2 = 0000 0001 (binary~
and the contents of CREDH+3 - 0000 0000 (binary). ~PU 11 thus detects a leading zero, which it masks b~ storing the data OF in PIA5A. The most significant digit of dis-play 15a lS selected b~ MPU 11 storing the data 08 in PIA4AD.

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This causes line PA3 o~ chip PIA4 to be Hiyh and therefore the output of inverter 52 to ~e Low. Because of the mask-ing of leading zeros, however, no di~..t is aisplayed.
Next, ~IPU 11 examines the ne~t four bits of bu~-fer CREDH+2, finds their value is non-zero and displays ~ . -their value by supplying the data 01 to PIA5AD and the data 04 to PIA4A~ The signal to chip PIA4 causes line PA2 thereof to be EIigh, which selects the second MSD of display 15a. The numeral "1" is therefore displayed in the second MSD of display 15a. MPU 11 then detexmines the value o~ the contents of the hiyhest four bits of buEf~r CREDH~3 an~ causes it to ~e displayed by supFlyins the da-ta 00 to PIA5D and the data 02 to PIAgD, the first to cause the numeral "0" to be displayed, the second through gate 78 and inverter 50 to select the second LSD of the display. Finally, MPV 11 determines the value of the least four bits of buffer CREDH+3 and causes it to ~e displayed in the LSD of display 15a by supplying the data 00 to PIA5AD and the data 01 to PIA~AD.
~ine PA2 of chip PIA4, in addition to being used to select the second MSD of display 15a, is also used to refresh the decimal point.of display 15a. To refresh the decimal point ~IPU 11 causes line PA2 to be High and also causes line PA5 of chip PIA5 to be High.
25 The High on line PA5 of chip PIA5 is supplied throuyh pin 32 of plug P2 to an inverter 369 (Fiy. 15), the out-put of which is connected to the base of PNP transistor Q37, the collector of which is connected to the decimal point of display 15a. When line PA5 yoes High, the out-30 put of inverter 36~ goes Low and transistor Q37 conducts.
. ', If line PA2 of chip PIA4 is High at the same kime, a cir-cuit is completed from transistor Q37 through the decimal point of display 15a to inverter 51, which refreshes the decimal point.
Consequently, shortly after the custo~er deposits his dollar coin in vendor 1, display 15a displays "1.00", i.e., his credit. This display, with the decimal point, is continuously refreshed. Thus, MPU 11 is responsive to control circuit 7 being in the vending mode and to the ~ ~ -deposit of money in vendor 1 to determine the amount of credit accumulated as a result of -the deposit and to sup-ply to display means 15 a signal corresponding to th~
accumulated credit, which credit display circuit 15 thex~-upon displays. Also, it is clear that display 15 comprises a plurality of display units, each of which is adapted to display one digit of the customer's accumulated credit.
After the customer deposits the dollar coin into vendor 1, suppose he also deposits a quarter. Quarter indicator cixcuit 133 (Fig. 23) will then supply a Eligh through pin 32 of plug Pl to peripheral data line PA5 of chip PIA3 tFig~ 12) and a spike throuyh pin 20 of plug Pl to the CBl input of chip PIA3. The ~igh input causes the IRQB pin of chip PIA3 -to go Low. This IRQB pin, like all those of control circuit 7, is connected by line L117 to the IRQ input of MPU 11. Therefore, the deposit of a quarter generates an interrupt. MPU 11 goes through the same sequence of program steps described before but, in-stead of finding a dollar coin interrupt, it continues executing the program and finds a quarter interrupt hy reading PIA3BC. MPU 11 updates the customer's credit by storing 25 in buffer CREDH+3 and updates the number of quarters buffer b~ one, making FEQ~AR = 01. In exactly the same manner as in the case of the dollar coin, MPU 11 updates the display of the customer's credit on display 15a. This time, however, the contents of CREDH~3 are no longer zero, but are rather "25" so the next to the last numeral displayed will be "2" and the numeral displayed in the LSD of the display will be "5". At this point, the cus-tomer has accumulated $1.25 credit.
~Ie inserts another quarter. MPU 11 responds exactly as in the case of the first quarter, except that it updates the contents of buffer CREDH+3 to 50 and the contents of number of quarters buffer FEQUAR to 02. Note that prior to the deposit of this second quarter, the con-tents of buffer CREDH+3 was 0010 0101 (binary). MPU 11 adds 0010 0101 (binary) to this figure to obtain 0100 1010 ~binary), which is 4A in hexadecimal notation, and then conver-ts this binary figure to 0101 0000, the BCD repre-sentation of 50 (decimal). It is this representation of the customer's credit that is stored in buffer CREDH+3.
MPU 11 then updates display 15a to reflect the customer's new total credit.
The customer then deposits a third quarter. In response MPU 11 updates credit buffer CREDH+3 to 75 and ~!
the number of quarters buffer to 03 . The customer's total credi-t is now $1.75, which is sufficient to buy item 3i, ~3~ 9 which costs only $1.55. The customer looks at display l5a, having forgotten how much money he has put in, sees ~ -he has enough money to buy item 3i and presses selection switch 13i tFigs. 1 and 15). ;
Before discussing item selection, it should be pointed out that, although the above example of credit handling and coin identification concerned only dollar coins and quarters, MPU 11 handles these functions for dollar bills, dimes and nickels in substantially the same way. The only real differences are in the particular peripheral data lines of chip PIA3 that go High upon the detection o a specific coin and in the specific PI~
interrupt inputs tCAl or CBl) th~t generate the interrupt.
When a nickel is detected, peripheral data line PA7, con- ;
nected throuyh pin 34 of plug Pl to nickel indicator cir-cuit 12~ (Fig. 23) goes High, as does the CAl input of -chip PIAl, which is connected to circuit 129 through pin 9 of plug P2. When a dime is detected, the peripheral data line that goes High is line PA6. Line PA6 of chip PI~3 is connected through pin 33 o~ plug Pl to dime indicator circuit 131. The detection of a dime also causes the CBl input o chip PIA5, which is connec-ted through pin 38 of plug P2 to circuit 131, to go High. Finally, the detection of a valid dollar bill causes line PA3 of chip PIA3 and the CAl interrupt input of chip PIA2 to go High. Line PA3 is connected to dollar bill indicator circuit 123 through pin 30 of plug Pl while the CA1 pin of chip PIA2 is connected thereto through pin 22 of plug Pl.

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From the above description of the standby sub-l-oUtine FIRTSl and the subroutine DISPLY contained therein, it should be clear that when ~IPU 11 is no-t servicing an interrupt it is continuously sequentially activating, or attempting to activate, the digits of displays 15b and 15a. As a result, every few microseconds pin 5 of plug P2 goes High. Shortly thereafter pin 4 of plug P2 goes High, and shortly after that pin 3 of plug P2 goes High.
Pins 2, 17, 16, 15 and 14 in their turn also go High, and after MPU 11 causes pins 33 and 34 of plug P2 to go Hi~h the cycle repea-ts. Pins 2-5 and 14-17 of plug P2 are connec-ted to gates 77-84 (Fi~. 16) which are in turn connected to selection switches 13. When the cus-tomer presses selection switch 13i, therefore, the momen-tary ~ligh output of gate 78 is supplied througll switch 13i and resistor R22 to ground and through that switch and resistor R29 to NOR gate Gl9. The resulting Low output of gate Gl9 is supplied on line L69 to gate 95 (Fig.
17) and from there to NOR gate G21. The other input to gate G21 is also Low since mode-setting switch 98 is in the vend position, so the output of gate G21 is a High. $
This High is supplied through pln 35 of plug P2 to the CBl input of chip PIA4 (Fig. 13), which causes the IRQB
output of chip PIA4 to go Low. This Lowv as explained above, is supplied on line L117 to the IRQ input of MPU
11 and in response thereto MPU 11 initiates an interrupt sequence by jumping to subroutine INTERP.

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As in the case o~ the coin generated interrupts~
MPU 11 first checks for a time-base clock 113 interrupt, next for a spe~d-sensor-clock 107 interrupt, and then for coin/currency interrupts. This -time the search for a cOin/
interrupt is also unsuccessful, so MPU 11 performs the next step in subroutine INTERP, which is to determine i the interrupt was a selection interrupt. To identify a selection interrupt, MPU 11 reads PIR4BC and tests bit 7 thereof to see if it is Eligh. Bit 7 was set High when the CB1 input ~c~s of chip PIA4 went High, so MPU ll~b~ee~ to the selection subrou-tine SELl. In subroutine SELl MPU 11 first clisables s~veral inter.rupts, including the selection .in~errupt from chip PIA~, by loading the data 04 into PI~4BC (d.isabling the selection interrupt), PIA6BC (disabling the credit re-call interrupt), PIAlBC (disabling the clear total sales interrupt), and PIA6AC (disabling the coin tube payout request interrupt).
Next MPU 11 determines which selection switch has been closed by strobing the peripheral data lines of PIA4A
and reading the peripheral data lines of PIA4B. Toge-ther with selection switches 13a-13x, PIA4A and PIA~B constitute means for supplying a vendor status input indicating the selection of an item 3 to MPU 11. Data lines PA0-PA7 of chip PIA4 are connected through pins 14-17 and 2-5 of plug P2 and gates 77-84 to the rows of switch matrix 76, which consists of selection switches 13a-13x and switches 60-71, 73 and 74 Data lines PB0-PB5 of chip PIA4 are con-nected through gates 86-91 and resistors R27-R32 to 9~

the columns of that matrix. MPU 11 can thus detect which selection switch, or other switch in matrix 76 for that matter, has been closed simply by determining the pair of lines, one from lines PA0-PA7 and the other from lines PB0-PB5 that have a circuit comple-ted through them. For example, MPU 11 first causes line PA0 of chip PIA4 to go High. This High is supplied through pln 14 of plug P2 and gate 77 to switches 13a-13f. MPU 11 then reads lines PB0-PB5 of chip PIA4. sut since none of switches 13a-13f are closed, the outputs of gates 86-91 are all Low, so lines - PB0-PB5 are also all Low. MPU ll then causes line PAl to go High, by storing the data 02 in PIA~A. This Eligh is supplied through pin 15 of plug P2 and gate 78 to switches 13y-131. Since switch 13i is closed the High is further supplied through resistor R29, gate 89 and pin 43 of plug P2 to data line PB2 of chip PIA4. MPU 11 reads PIA4B and thereby detects the High on line PB2, indicating a switch closure in the third column. It stores this in~ormation in the selection buffer SELINF+l by loading the data 04 therein and stores the row information by storing the data 02 in buffer SEI.INF. Having found the closed switch and stored this information in the appropriate buffers, MPU 11 does not continue testing for switch closures but instead jumps to subroutine SEL06.
In subroutine SEL06, MPU 11 determines the posi-tion number of the item selected. The position number of item 3a is "01" J that of item 3b is "02", that of item 3g is "07" and so forth. The position number of item 3i, the :

selected item, i5 "09". The address in chip EAROMl where 'che prices are stored corresponds to the particular posi~
tion numbers of the items. For example, the price of item 3i is stored in address "09" in chip EAROMl. In determin-ing -the position number of the selected item, MPU ll stores the selection's column information in buffer HORSOL, i.e~, HORSOL = 04, and the row information in buffer SELECT, i.e., SELECT = 02. MPU 11 stores the position number of the selected item in one of its accumulators. MPU ll then jumps to subroutine READ02 to find the price of item 3i.
In general, MPU 11 reads the price of item 3i, or any item for that matter, by supplying the address of that item to chip EAROMl, setting Ihe EAROM in the read mode alld selecting it, clocking the EAROM, and then reading the price of the item from PIAlB and PIA6B. Specifically, in subroutine READ02, MPU 11 first clears control registers PIAlBC and PIA6BC
which allows it to set PIAlB and PIA6B as inputs by storing the data 00 into data direction registers PIAlBD and PIA6BD.
Next, the microprocessor programs the CB2 pin of chip PIAl to be an output by storing the data 34 in PIAlBC. This CB2 pin is used to clock chip EAROM1. The data 04 is stored in control register PIA6BC. As a result of this and the storing of the data 34 in PIAlBC, MPU 11 subseq~ently addresses the peripheral registers PIAlB and PIA6B when it reads those chips rather than their data direc-tion registers. Chip EAROMl is put into the read mode by having a High on pin 25 and a Low on pin 26. These pins are connected by lines L68 and L66 to pins 8 and 7, the PA6 and PA5 peripheral data lines, of chip PIAl. To select chip EAROMl and put it in the -read mode, MPU 11 supplies 110X XXXX (binary, where 'IX" means the signal level can be High or Low) to PIAlA. This causes peripheral data line PA7 (pin 9) of chip PIAl (E'ig. 6) to .
7~

~3~91g be High, which Hlgh is supplied on line Lll9 to NAND gate G35 (Fig. 8) causing its output -to go Low, which causes the output of inverter 365 to go High, thereby putting a High on pin 27 of chip EAROMl (Fig. 7), which selects that chip.
It also causes line PA~ of chip PIAl to be High and line PA5 to be Low. These voltage levels are supplied over lines L68 and L66 to pins 25 and 26 of chip EAROMl, thereby putting it in the read mode. ~lPU 11 also stores the address of item 3i, i.e., 09, in PIAlA, which causes that address to be supplied to the address pins (pins 19-23) of chip EAROMl o~er lines AOf-A4f. Having supplied the proper address to chip EAROMl, MPU 11 then clocks it by supplyiny the data 3C to PIAlBC. This causes the CB2 pin (pin 19) of chip PIAl (Fig. 6) to go High.
That High is supplied on a line L139 to the clock input (pin 18) of chip EAROMl (Fig. 7). The clock pulse is removed by MPU 11 supplying the data 34 to PIAlBC. Shortly after being clocked, chip EAROMl supplies the eight LSBs (least signifi-cant bits) of the price of item 3i to its pins 28, 1-6 and 8 and the eight MSBs (most significant bi~s) to its pins 9-16.
MPU 11 then reads the aight MSBs by reading PIA6B, whose peripheral data lines are connected to pins 9-16 of chip EAROMl through lines L51, L53 . . . L65, and stores this value, i.e., 0000 0001 (binary)j in the buffer COSTH. MPU 11 reads the eight ~SBs by reading PIAlB and~stores this value, i~e., 0101 0101 (binary), in the buffer COSTH~1. Thus MPU 11 is responsive to a signal indicating a selec-tion to recall the price of that item from memory 9.
After obtaining the price information for item 3i, MPU 11 jumps to the negotiate subroutine, NEGTSK, where it determines if the customer has sufficient credit to buy the item selected. ~U ll's first step in subroutine NEGTSK is to check free vend switch 199 (Fig. 29) to see if it is ~3~9-1~

closed. It does this by reading PIA5B and dete~mining if line PB0 thereof is Low or High. Assuming a serviceman has not closed free vend switch 199, line PB0 of chip PIA5 will be High because the output of gate 201 (Fig. 29) to which line PB0 is connected through pin 22 of plug P2, is High whenever the free vend switch is open. Since line PB0 of chip PIA5 is High, MPU 11 proceeds wlth the NEGTSK subroutine.
If it had been Low, MPU 11 would have cleared buEfers COSTH
and COSTH~l, ensured that the customer would receive all his credit back, and jumped to the vending subroutine VENTSK.
Since free vend switch 199 was not closed, MPU
11 next checks to see if the price for i-tem 3i s-tored in chip EAROMl is 00. This is an anti-jackpot feature oE
control circuit 7 which protects against -the vending of items if the price for those items stored in chip EAROMl is zero. If the price stored in chip EA~OMl for item 3i were zero, MPU 11 would exit the interrupt sequence through a subroutine NEGT03 in which it would reestablish the cus-tomer's credit and go to standby, i.e., subroutine FIRTSl, to await the customer's next command. Since cost buffers COSTH and COSTH+l contain a non-zero price for item 3i, MPU 11 proceeds to the nex-t task of subroutine NEGTSK, which is to de-termine the difference between the customer's credit, contained in buffers CREDH+2 and CREDH+3) and the item's price, which is contained in buffers COSTH and COSTH+l. This is accomplished in subroutine SUBTSK. If the customer's credit equals the cost of the item selected, which it does not in our hypothetical case, MPU 11 then upd tes the credit buffers by storing 00 in them, i.e., CREDH~2 = 00 and CREDH+3 = 00, and jumps to the vend 9i~3 subroutine VENTSK. If the customer's credit is less than the cost of the item selected, MPU 11 reestablishes the customer's credit in buffers CREDH+2 and CREDH~3 and exits to the standby subroutine FIRTSl to await anot~er command. This would be the case, for instance, i the customer had deposited only $1.50 before pressing selec-tion switch 13i.
If the customer's credit is greater than the price of the item, which is the present case, MPU 11 stores the difference, i.e., 20¢, in buffers CREDH+2 and CREDH~3 as the customer's remaining credit. This t of course, is stored as CREDH~2 = 00, CREDH~3 = 20. Before proceeding to vend item 3i, MPU 11 checks the nickel and quarter change tubes to see if they are empty by r~ading PIA3B. As explained above, if both these tubes are empty, the output of AND gate G25 in circuit 153 tFig. 24) is Low. This Low is supplied through gate 169 and High.
This High is supplied through amplifier 169 and pin 12 of plug Pl to peripheral data line PB7 of chip PIA3.
If this line is Low, MPU 11 does not allow vending of item 3i because payback of change could not normally be made, and it returns the customer's credit in the full-escrow mode to a coin return cup CP.
Assu~ing the nickel and quarter change tubes are not empty, MPU 11 checks line PAl of chip PIA3 (Fig. 12) to see if the dollar change tube is empty. As explained above, if the dollar change tube is empty, the output of gate 165 (Fig. 24) is Low. This Low is supplied through pin 28 of plug Pl to line PAl of chip PIA3. If g:~9 that tube is empty, MPU ll detects this Lo~ on lirePAl and in response checks to see if the change that would have to be re-turned to the customer aEter vending exceeds $2.00. If so, ~U 11 returns the customer's credit and exits to standby as above. If line PAl of chip PIA3 is High, on the other hand, indica-ting that the dollar coin tube is not empty, MPU 11 checks to see if the customer would re-ceive over $5.00 in change after a vend. If so, the cus-tomer's credit is again returned to coin cup CP. The pur~
pose of these $2.00 and $5.00 limitations is to keep the change tubes from being emptied by some unscrupulous cus-tomer. Clearly. the present example falls within all the limits set orth above. MPU 11 in this case sets status flag FLG5 = 20, which indicates that when change is made it should be with the least possible number oE colns, and jumps to the vend subroutine VENTSK.
The first thing MPU 11 does in subroutine VENTSK
is to set its interrupt flag so that no other interrupts can cause an interrupt sequence while vending is taking place. Then it checks the status of vendor 1 by jumping to subroutine MACSTA described above. To recapitulate, in subroutine MACSTA MPU 11 determines if the elevator is at delivery station 105. Assuming for the moment that the elevator is not at the delivery station, MPU ll exits through a subroutine NEGT03 to standby to await further customer commands, such as credit recall. The credlt re-call interrupt is described in full infra.

, 1~3~919 ~ `

If the elevator is at delivery sta~ion 105, the status of vendor 1 is "go" so l~PU 11 proceeds with.the ~ubroutine VENTSK. MPU 11 checks status flag FLG7 to see if the anti-jac~pot delays (AJDs) for the coi~s have ex-pired to ensure that no i~em is delivered un~ he AJDs for the coins have elapsed. If the AJDs have not elapsed, MPU 11 exits subroutine VENTSK through NEGTO3 to standby.
If this were the case, our customer would have to press selection switch 13i again for vending of i~em 3i to occur.
lU And this action would re-initiate the above sequence.
Assuming that the AJDs have all expired, MPU 11 then checks the buf~ers SELECT and E~ORSOL for zero contents.
If the contents of either are zero, an error has occurred, and MPU 11 would exit through NEGTO3 to standby. However, in our example, SELECT = 02 and HORSO~ = 04, so MP~ ll does no-t exit subroutine VENTSK but instead disables the CRE21 by causing line PB6 of chip PIA3 to go Low. Line PB6 is connected through pin 13 of p}ug Pl to CRE~-energi2ing circuit 177 (Fig. 26). A Low at pin 13 o~ plug Pl causes line L93 to be High. As a result the C~EM has no ground path and it is deenergized, which inhibits any new coins rom entering the coin unit - they are deflectsd to coin cup ~p, MPU 11 next, in subroutine DISINT, disables all the interrupts except the time-base-clock 113 interruPt by ~toring ~he data 04 in control registers PIAlAC, PI~lBC, PIA~C, PIA2BC, PIA3AC, PIA3BC, PIA4BC, PIA5BC, PIA6~C
and PIA6BC. Also, all present interrupts are cleared in sub-routine CLRINT, explained above.

,, a3 ~3~91~

Up until this point any dollar coin or bill was being held in its escrow position pending the determination that a vend would occur, so that if the vend were aborted, the customex's o~ coins or bill~-could be returned to him.
After disabling and clearing the interrupts, MPU ll accep-ts an~ dollar coins or bills into their s~orage positions, since the vendor status is now "go" for a vend~ If a dollar bill had been deposited by the customer, it would now be moved into its storage position from its escrow position by MPU 11 supplying the data OC to PIA~A. This causes lines P~2 and PA3 of chip PIA6 (Fig. 6) to go High. Line PA3 is connected through pin 45 of plug Pl to dallar-bill-accept circuit 195. As explained above, when pin 45 oE
plug Pl goes High, line LlOS of circuit 195 goes Low and the validator moves the dollar bill to the storage position.
By supplying the data OC to ~IA6A, ~U ll also accepts the dollar coin (or coins) deposited by the cus-tomer. The High on peripheral data line PA2 of chip PIA6 is supplied through pin 43 of plug Pl to dollar coin escrow circuit 173. This causes line L89 to go High, deenergizing the dollar coin escrow solenoid in the coin changer. The dollar coin, upon the deenergization of the dollar coin escrow solenoid, falls from the escrow position to the coin box.
After a slight delay, to give the validator time to move the dollar bill, if present, to its storage loca-tion, MPU ll removes the signal to the validator b~ storing the data F7 in PIA6A. This causes line PA3 o~ chip PIA6 to go Low.

~PU 11 now begins control of the elevator.

First, it stores the contents of buffer SELEcTt i.e.~
02, in P.1~2A, ca~lsing lines PA0, PA2 and P~3 of chip PIA2 to be Low and line PAl to be ~ligh. Lines PA0-~A3 are con-nected to pins 2-5 of plug Pl respectively, so this ca~lses a ~igh to be supplied to one side of s~itch 293 (Fig. 34) wh1le s~itches 291, 295 and 297 remain Low. Then it stores 04, the contents of the buffer HORSOL, in PIA2~ causing lines PB0, PBl, P~3, PB4 and PB5 of chip PIA2 to be Low ln ~lnd line PB2 to be High. Lines PB0-PB5 are connectecl to pins 35-40 of plug Pl, so the High on line PB2 causes pin 37 oE plug Pl to be High also. As explained above, this en~xcJizf-~ HORSOL 253, the horizontal solenoid ~ssociated with tne third column from the left of items 3 in vendor 1.
The microprocessor then sets the up-~ode flag, i.e., it sets F~G6 = 40, and enables speed-sensor-clock 107 (Fig. 19) and time-base-clock 113 (Fig. 20) interrupts by storing the ~ata lC in PIAlAC and by storing the data 07 in PIA4AC.
Storing lC in PIAlAC ensures that when the CA2 interrupt ;nput o~ chip PIAl ~Fig. 6) goes Hi~h the IRQA output of chip PIAl will go Low, generating an interrupt sequence.
The ~A2 input is connected through pin 8 of plug P2 to circuit 106. Every time that the elevator motion sensor generates a pulse, the output of gate 109 in circuit i06 goes High. This High is supplied through pin 8 of plug P2 to the CA2 input of chip PIAl and causes an inter-rupt. The enablirlg of the time-base-clock 113 interrupt has already been explained.

' ~ 11 now enters a subroutine, V~ND12, ln which it refreshes displays 15a and 15b. It stays in -this subroutine until the first time-base-clock iIter-rupt, at which time it jumps to subroutine INTERP where it determines by reading bit 7 of PIA4AC that time-base-clock 113 caused the interrup-t. MPU 11 then examines the status ~lag FLG6 to determine if it should perform its elevator control function. Since FLG6 - 40, MPU 11 is in an elevator control mode, and it jumps to elevator control subroutine TBC10. At this point in the vend cycle, MPU 11 checks whe~her the ~levator is at delivery st~.t.ion 105 by ~sirg suhroutine ~IACSTA, described above.
Since the elevator is at the delivery station, MPU 11 then tests to sea if door ~7 i9 closed by reading PIA2A
and testing line PA7 thereof. Line PA7 of chip PIA2 is connected through pin 9 of plug Pl to the output of gate 237. If the elevator is at the delivery station and door 117 is closed, this output will be High and line PA7 will be High. MPU 11 checks for this High and if it is not presen-t,does not proceed with the vend. Thi.s check is made to ensure that the elevator does not move unless door 117 is closed. MPU 11 then locks door 117 by deener-gizing door locX solenoid 223 (Fig. 31). The door lock solenoid is deenergized by the data DF being stored ln PIA2A which, inter alia, makes line PA5 of chip PIA2 Low.
Line PA5 is connected through pin 7 of plug Pl to door lock solenoid circuit 221 (Fig. 31). When line PA5 goes Low, solenoid 223 is deenergized. When this occurs, ~13~91~

switch 233 (Fig. 32) s~itches from the open to the closed position, supplying a High through gate 239 to pin 8 of plug Pl. Pin 8 of plug Pl is connected to peripheral data line PA6 of chip PIA2, so this line goes High also.
MPU 11 reads PIA2A and checks line P~6 to see if door 117 has been locked. If not, it exits the vend cycle.
If door 117 has been locked, however, MPU 11 proceeds to generate a vend signal. That vend signal is the data 10 and it is supplied by MPU 11 ~o PIA2A, causing line PA~ of chip PIA2 to go High. Line P~4 is connected t~ ~in 6 of plw~ Pl and so line P~4 ~upplies the ver.d , slcJnal to run relay circuit 241 (Fig. 33~ ener~izing run relay 2as. This causes power to be supplied to the ele-vator motor. As a result the elevator starts moving upwardly. Thus, MPU 11 in response to the selection or an item 3 generates a vend signal, provided, of course, tha-t there is a non-zero price associated in memory 9 with that item and also provided that the cus'~omer's accumulated credit is suf-ficient to purchase 2d the particular item 3 selected. It should also be apparent at this point that MPU 11 generates a vend signal even if the customer's accumulated credi~ is insuff^icient for purchase of the i~em selected if the free vend switch is closed in the i'on" position.
~5 Once it has energized run relay 245, MPU 11 initializes buffers TBC and SPEEDl~ ~hese buffers are used to determine whether the eleva-tor is moving or has stopped at a level. Buffer TBC is initialized ~7 3L1~3~919 with a value of 16 (decimal) and buffer SPEED1 is initialized with a value of 0. Buffer TBC is inltially decremented by one and every time time-base-clock 113 (Fiy.
20) interrupts, which is every 10 ms, it is again decremented by one. Buffer SPEED1 is incremented every time sPeed-sensor-clock 107 (~ig. 19) interrupts. ~hen buffer TBC
has been decremented to zero, i.e., after 150 ms, the value of the contents of buf~er SPEED1 is checked to see if it falls between 77 (decimal) and 100 (decimal). A
10 value within these limits indicates that the elevator is still moving. If the value is no-t within those limits MPU 11 removes power from the eleva-tor.
After initializing buffers T~C and SP~ED1, MPU 11 exits from the time-base-clock interrupt and xeturns 15 to the loop in subroutine ~EI~D12.
Every 1.5 to 2.0 ms while the elevator is moving, speed-sensor-clock 107 (Fig. 19) generates an interru~t by causing the output o gate 109 to go Righ.
MPU 11 in response u~dates buffer SPEEDl by one and exits 20 from the interrupt. Every 10 ms, time-base-clock 113 (Fig.
20) generates an interrupt in response to which r~u 11 decrements buffer TBC by one and exits that interrupt.
These interrupts continue to occur until buffer TBC is incremented down, i.e.,~decremented,to 3ero, at which 25 point MPU 11 tests to see if the value of the contents of buffer SPEEDl falls within the above-specified limits.
If so, it resets buff~r TBC to 16 (decimal~ and buLfer SPEED1 to zero.

~3Q~ ~

The elevator is moving up con-tinuously while the bufEers SPEEDl and TBC are being upclated. The speed of that movement is of course reflected in the fre~uency of interrup-ts from speed-sensor-clock 107 ~Fig. 19). As the elevator approaches level D, it closes switch 297 (Fig. 34) but nothing happens as a result of that closure because pin 5 of plug Pl is not High. Likewise, as the elevator approaches level C it closes switch 295 but nothing happens. However, as i-t approaches level B, it closes switch 293 which provides the High on pin 3 of plug Pl to line L109 and gate 299.
The out~ut of gate 299 is therefore hi~h ~nd this High is supplied on line Llll to NAND cJate G31 tFig. 35).
As described above, this causes vertical stop sole-noid 305 to be energized which stops the elevator at level B. Because the elevator has now stopped, the speed of the elevator motor changes, i.e., stops, and the speed~5ensor-clock interrupts now occur at a rate lower than 77 per 150 ms. MPU 11 detects this by comparing the value of the contents of bufer SPEEDl with the above-mentioned predetermined range of values and in response deenergizes run relay 245 (Fig. 33) by removing the vend signal. Specifical-ly MPU 11 changes the voltage of line PA4 of chip PIA2 from High to Low by storing the data EF in PIA2A.
Thus, MPU 11 is responsive to the number of pulses sup-plied from speed-sensor-clock 107 (Fig. 19) and circuit 106 durlng sixteen interrupts of time-base-clock 113 ~9 (Fig. 20) not falling within ~he predetermined range of 77 to 100 to remove the vend signal.
As shown in Canadian Patent No. 1,099,238, the stopping of the elevator at a particular level causes the tray motor to dispense the item at that level whose horizontal solenoid has been energized~ In the present example, HORSOL 253 was energized and the elevator stopped at level B, so item 3i is conveyed onto the elevator.
After MPU 11 deenergizes run relay 245, it exits from subroutine VEND 12 and enters a subroutine VEND 16 where it refreshes display 15a and 15b while waiting for the tray motor to reach its 180 position.
When the tray motox reaches its 180 position it stops and pin 42 of plug Pl ~Fig. 36) goes High, as discussed above. Pin 42 o~ plug Pl is connected to peripheral data line PB7 of chip PIA2, so this line also goes High when the tray motor reaches the 180 position~
MPU 11 reads PIA2B and checks line PB7 every time it goes through subroutine VEND 16, so when the tray motor has conveyed item 3i onto the elevator MPU 11 detects that fact, i.e., that the tray motor has reached the 180 position, and sets status flag FLG6 = 08, indicating that control circuit 7 is now in the elevator down mode.
The energization of relay N (Fig. 36) in response to the tray motor reaching its 180 position switches the elevator motor to the down mode but that does not simultaneously cause the elevator to ~ .

~3~919 descend. First, MPU 11 must cause run relay 245 to be energized. Rather than go to that step immediately, however, MPU 11 first starts to gi~e the customer his change. Specifically, MPU 11 checks buffers CREDH-~2 and CREDH+3 to see if the customer is due any change. If not, MPU 11 proceeds immediately to the elevator control section of the program~ But in our example, the contents of CREDH+3 = 20, i.e., the customer should recelve 20¢ change.
MPU 11 then stores A0 in number-o~-coins buf~ers FENIC, FEDI, FEQU~R, FEONEC, FEONEB, and FETWO, stores the data 08 in -the bufer CONTYP, and jumps to subroutine MONTSK. Buffer CONTYP is used as a pointer for MPU 11 to use in subroutine MONTSK to keep track of what type coin is being paid to t~e customex. In subroutine MONTSK, MPU 11 first deter-mines if the value of a doller coin is less than or equal to the customer's credit, which is stored in bu~fers ~REDH+2 and CREDH~3. Since the dollar is of greater value than the customer's credlt, i.e., 20¢, MPU 11 updates the contents ~uffer CO~TYP to polnt to quarters by making its contents 04. Then the same check is made with the quarter. Since this is also greater than the customer's credit, MPU 11 updates the pointer buffer to CONTYP = 02 which indicates that dime coins are now to be tested.
Since a dime is less than 20~, MPU 11 can proceed with making change.

9'l .

9~9 To make change in the least coins mode, MPU 11 reads PIA3A to see if the dime change tube is empty. Line PA0 of chip PIA3 is connected through pin 27 of plug Pl to the output of ga~e 167 (Fig. 24). As explained above, this output is Low when the dime chan~e tube is empty. If MPU 11 detects a Lo~.~ on line PA0 of chip PIA3, it switches to the nickel coin tube by updating the pointer buffer to CONTYP = 01. Similarly, if the change due the customer exceeds 51.00, MPU 11 checks whether the dollar coin tube is empty by reading PIA3A.
Line PAl of chip PIA3 is connected through.pin 28 o:E plug Pl to the ou-tput of yate 165 (Fig, 24) and this output is Low when the dollar tube is empty~ In that case, ~PU 11 would switch to the quarter change tube from the dollar change tube by updating the. pointer buffer to CONTYP = 04.
Return}ng to our example where the customer is to receiVe. 20~ in ch2n~e~ i~ the dime tube is not empty CONTYP = 02. If it is~ CONTYP = 01. In any case MPU 11 stores the value of CONTYP in PIA3B
which. causes a coin to be ejected from one o the change tubes, Lines PBO-PB3 of chip PIA3 are con-nected through.pins 19, 18, 17 and 16 o~ plug Pl to the coin ~eturn portion of circuit 153 (Fig. 24).
As explained above~ a High on pin 16 (.and thus on line PB3) causes a dollar coin to be ejected from its coin tube, a High on pin 17 (.and thus on line PB2) .

.

g~

causes a quarter to be ejected, a Hi~h on pin 18 ~i.e., on line PBl) causes a dime -to be e.jected, and a High on.pin 19 (on PBO) causes a nickel to :~
be ejected. When MPU 11 stores the cont:ents of .
buffer CONTYP in PIA3B thereforer it causes line PBl (.or line P~Q if the dime tube is empty) to - ' go High~ thereby ~iving the customer one dime in .~ -change.., MPU 11 also updates the customer's credit to 10¢, by updatin.~ hu~Ee.r CRE.D~3 to 10 MPU 11 then stores the data OF in buffer PAYBKl.~ Bu~ex P~YBKl is us,ed to~ether with buffer TBC to keep the payback solenoids in the coin handler on fo~ 150. ~ss Qf course~ if those solenoids need to be energized for a. different length o~ time than 150 ms, the initial contents of buffe~ PAyBKl should be changed ,~ :
a,ccordingl~., A~ter initia,lizing buffer PAYBKl, MPU 11 , enabl.e$ inter,r,upts frorn time-base.~clock 113 and ':, spe.ed-senso~cl.ock 107 in subroutine VENDOA as described above and then refreshes displays 15a and '~
15b in subroutine. ~END31~
At the. first interrupt from tim,e-~ase.-clock 11.3 (.F,ig.~ 2Ø),,~ MPU 11 ener~i.ze.s. run relay 245 (Fig. ..
33) and the. eleya,to~ starts back. down toward delivery s-tat,~,on.10~S After fi.f-teen. of these. interrupts, the con.tents ~ bu~fer PAYBKl are reduced to zero and the payback rel,ay is deenergized hy M~U 11 clearlng PIA3B.., A~ter another s.hort delay MPU 11 causes another d;m,e. to be giYen to the customer in change, ~3~

followiny exactly the same s-teps as outlined above for the first time, and updates CR~DH~3 = 00 since :
the customer has no remainin~ credit.
~lPU 11 now continues refreshing displays 15a and 15b and checking the elevator motor speed until the elevator reaches delivery s-tation 105.
At that time, MPU 11 deenergizes run relay 245 (Fig. 33) and then tests, by read.ing line PB4 of chip PIA5, to see if the elevator is at delivery station 105. I.ine PB4 is high if the elevator is at the delivery station. This high on line PB4 o chip PI~5 at this point in the vendincJ cycle is a control input siynal indicatin~ to MPU 11 the vend.ing of item 3i, and switch 229 and chip PIA5 together constitute means for supplying MPU 11 that signal.
In response to the signal that the selected item has been vended, MPU 11 clears and disables all interrupts ~ :
(in subroutine DISINT) and updates the total sales figure in chip EAROMl (.in a subroutine SALINV).
In subroutine SALINV, MPU 11 first .reads the accumulated total sales figure from addresses lD
and lE in chip EAROMl as before and stores this in buffers CREDH, CREDH-~l, CREDH+2, and CREDH-~3. Since the total accumulated sales figure before this last sale was $1a. 95l CREDH = 00, CREDH+l = 00, CREDH~2 =
10, and CREDH+3 = 95. MPU 11 adds the cost of item 3i to this and updates CREDH~2 to 12 and CREDH~3 to 50.
These figures are then stored in buffers INVO4, :
INVO4+1, INVO4+2 and INVO4~3, and are written into addresses lD and lE in chip EAROMl.
MPU ll writes-the new total accumulated sales figure in chip EAROMl in subroutine LDPR07 The first step in writing the new total accumulated sales figure in chip EAROMl is to erase the old figure stored there. MPU 11 does this by addressing location lD as before through chip PIAl and putting chip EAROMl in the erase mode by causing line PA6 -of chip PIAl to be Low and line PA 5 thereof to be High. This causes chip EAROMl's mode con-trol input Cl ~pin 25) to be Low and its mode control input C2 (pin 26) to be High, which is the proper combination to put chip EAROMl in the erase mode and the data at location lD is erased. MPU 11 then initializes PIAlB and PIA6B as outputs by storing the data FF
in their data direction registers, i.e., PIAlBD and PIA6BD, to write the four most significant digits o the new total accumulated sales figure in location lD of chip EAROMl. Chip EAROMl is then put in the write mode by causing its Cl and C2 inputs to both be Low. The irst two most significant digits of the new total sales figure are supplied by MPU ll to PIA6B and are thereby written in the highes-t eight bits of location lD. The next two most significant digits, i.e., the contents of buffer CREDH+l, are supplied by MPU 11 to PIAlB and are thereby written in the lowest eight bits of location lD. MPU ll then proceeds in exactly the same way to erase the old figure at location lE and to wri-te the contents of buffer CREDH+2, i.e., 12, in the highest eight bits of location lE and the contents of buffer CREDH-~3, i.e., 50, in the lowest eight bits.
After storing the n~w total accumulated sales figure in chip EAROMl, MPU 11 returns -to the standby loop FIRTSl. Part oE that loop is the in-struction JSR PROSEN which causes MPU ll to jump to subroutine P~OSEN to check for an item on -the elevator. In subroutine PROSEN, MPU ll checks once again to see if the e}evator is at delivery station 105 by checking line PB4 of chip PA5 which i5 con~
nected to elevator position indicator switch 229.
If the elevator is at delivery station 105, MPU ll checks product sensing circuit 99 (Fig. 18) for circuit failure by testing lines PB2 and PB3 of chip PIA5. These lines are connected through pins 24 and 25 of plug P2 to the collectors of photo-transistors Q3 and Q5 (Fig. 18). Since LEDs 101 and 103 are normally off, the collectors of photo-transistors Q3 and Q5 are normally High. Therefore, if lines PB2 and PB3 of chip PIA5 axe Low, MPU ll knows that product sensor circuit 99 has failed.
Once circuit 99 has passed its test, MPU ll checks line PA6 of chip PIA2 to see if it is High. If it is, that indicates that switch 233 (Fig. 32) is closed and, therefore, door 105 is closed and locked.

ilaviny determined that door 105 is locked, MPU senses whether item 3i is on the elevator ~y supplying the data XOXX XXXX (binary) to PIA5B.
This causes line PB6 of chip PIA5, which line is connected through pin 12 of plug P2 to gate 367 ~ -~Fig. 18), to go Low. As a result, transistor Q35 (Fig. 18) conducts, causing LEDs 101 and 103 to light. If-item 3i is present on the elevator, ligh-t from LEDs 101 or 103 will be obstructed and insufficient light will fall on the bases of ~-phototransistors Q3 and Q5 to turn them on. Depending upon the placement of item 3i on the elevator, both phototransistors may be off, transistor Q3 may be on and transistor Q5 may be off, or vice versa, but only if item 3i is not on the elevator will both phototransistors be on and conducting. MPU 11 thereore tests lines PB2 and PB3 of chip PIA5 to see if either is High. If one of these lines is High, the associated transistor is off and ~t-em~ 3i is on the elevator at delivery station 105~ If the product is not sensed on the tray, MPU 11 exits the subroutine. If item 3i is on the tray, however, MPU 11 supplies the data lXXX XXXX (binary) to PIA5B, causing the PB7 line of chip PIA5 to go High. This line is connected through pin 13 of plug P2 to gate 119 (Fig. 21).
When line PB7 goes High, transistor Q7 conduc-ts, energiziny coil 121 which, as explained above, causes door 117 to open. After opening door 117, MPU 11 turns off the product sensor LEDs, LEDs 101 .

-~13~3~19 and 103, by causing PB6 of chip PIA5 to go High.
MPU 11 then returns to its standby loop, sub-routine FIRTSl.
Every time MPU 11 goes through the DISPLY subroutine, which is part of the standby loop, it triggers a missing pulse detector, in dicated generally at 371 (Fig. 8), which is part of reset circuit 43. The purpose of missing pulse detector 371 is to cause control circuit 7 to reset if there has been a malfunction in the program.
Specifically, MPU 11 supplies the data XXXl XXXX
(~inar~¦ to PIA5A causing its PA4 line to ~ High, which starts a pulse. This High is supplied through pin 31 of plug P2 to missing pulse deteckor 371.
MPU 11 -then removes the High by causing line PA4 to go Low, which ends the pulse. As long as this pulse is supplled to de~ector 371 within a certain time, e.g., 3 ms, from the last such pulse, the output of detector 371 on a line L141 remains High. The period 3 ms is chosen to slightly exceed the maximum time MPU 11 should be executing instructions outside the DISPLY subroutine in the absence of a malfunction.
If a pulse is not detected within that maximum period, line L141 goes Low. This Low is inverted by an inverter 373 and the resulting High output is supplied to the base of an NPN transistor Q39 whose emitter is connected to ground and whose collector is connected to line L67. Transistor Q39 conducts, bringing line 9 ~3 . .

~.~ 30~19 L67 Low. We have already seen that a Low on line I.67 causes control circuit 7 to reset.
If the customer in the above example had de~
posited his $1.75 but then chosen not to select an item, he would press the coin return switch CRo This would ~ ~-cause a High to appear on line L94 of circuit 179 (Fig.
27), and pin 20 of plug P2 would go High as a result.
~ .
Pin 20 of plug P2 is connected to the CBl interrupt input (pin 18) of chip PIA6. Since chip PIA6 has been initiated to generate an interrupt signal whenever its CBl input goes High, pressing of the change return switch supplies an interrupt signal to MPU 11. Upon receiving this signal, MPU 11 jumps to the interrupt rou~
tine INTERP to identify the source of the interrupt. It discovers that the interrupt is a credit recall interrup-t by checking bit 7 of PIA6BC WhiCh is set High when the CBl input of chip PIA6 goes High. Having identified the inter-rupt, MPU 11 branches to credit recall subroutine RECAL.
In subroutine RECAL MPU 11 first disables all the interrupts and clears any present interrupts. It then checks status flag FLG7 to make sure that all anti-jackpot delays have expired. This is to prevent the return of credit until all coins deposited by the customer have been identified and added to his credit. MPU 11 then checks the customer's credit, which is stored in buffers CRED~I~2 and CREDH~3. If the credit is zero, MPU 11 exits the interrupt;
the customer is not owed any money. If the customer has some credit, MPU 11 disables the CRE~ by causing line PB6 of chip PIA3 to go Low.
.

-113~19 ;

MPU 11 returns the customer's credit in essen-tially the same manner as it made change. That is, buffe~r CONTYP is used as a pointer to indicate which bill or coin is to be returned and when a bill or coin is returned its number of coins buffer, e.g., FEDI, is decremen~ed by one.
The major difference between returning ~he customer's eredit in the full~escrow mode and making change is that in the former the contents of the number of coins buffers correspond initially to the numbers of coins or currency of each type that the customer has inserted into vendor 1 while in the latter the contents of those buffers are in-tialized with 160 (decimal).
In this example the contents of all the numbers oE coins buffers exeept FEONEC and FEQUAR are zero, FEONEC =
1 and FEQUAR = 3. MPU 11 Eirst ehecks buffer FETWO and initializes buffer CONTYP = 20. Since buffer FETWO is empty, MPU 11 updates CONTYP to point to dollar bills, i.e., CONTYP = 10. It then checks the contents of buffer FEONEB whieh is also empty.
If the eustomer had deposited a dollar bill in-to ' vendor 1, the contents of buffer FEONEB would equal 01 and MPU 11 would at this point return the bill by storing the contents of buffer CONTYP, i.e., 10, in PIA3B. Storing 10 in PIA3B causes line PB4 of ehip PIA3 -to go High. This . . .
Hlgh is supplied through pin 15 o plug Pl to circuit 193 (Fig. 28). As explained above, this High causes the vali- -aator to return the dollar bil~l from its escrow position to the eustomer.

3~

If the buffer FEONEB lS emp-ty, MPU 11 then updates the pointer to CONT~P = 08 and examines the con-tents of doll~r coin buf~er FEONEC. Since the customer deposited a dollar coin, the contents of this buffer are 01. MPU 11 stores the contents of pointer CONTYP~in PI~3B
and decrements the contents of buffer FEONEC by one. Stor~
ing the contents of the buffer CONTYP, i.e., 08, in PIA3B
causes the PB3 line o~ chip PIA3 to go High. This line is connected through pin 16 of plug Pl to change circuit 153. As described above, a High on this pin causes tran-sistors Qll and Q13 to conduct, resulting in the returnof a dollar coin to the customer. After returning the doll~r coin and decrementing the con-tents of buffer FEONEC

to zero, MPU 11 updates bufer CONTYP to point to quarters by changLng its contents to 04~ To see if any quarters need to be returned to the customer, MPU 11 examines the contents of buffer FEQUAR. Since the buffer FEQUAR has contents of 03, MPU 11 returns a quarter to the customer by again storing the contents of buffer CONTYP in PIA3B.
This causes line PB2 of chip PIA3, which is connected through pin 17 of plug Pl to the quar-ter return circuitry of circuit 153 (Fig. 24), to go High and one quarter is returned to the custome~. MPU 11 decrements buffer FEQ~AR

by one and again examines it for zero contents. Since buffer FEQUAR = 02 a~ this point, MPU 11 returns a second quarter to the customer and again decrements buffer FEQUAR
by one. This cycle is repeated one more time. MPU 11 re-turns the customer's third, and last, quarter and decrements ~3 .

buffer FEQUAR to zero. MPU 11 then updates pointer CONTYP
to point to dimes, i.e., CONTYP = 02 and examines the dimes number of coins buffer FEDI for non-zero contents. Since the customer deposited no dimes, bu~fer FEDI = o0 and no - 5 dimes are returned to him. If he had put dimes in vendor 1, of course, they would at this point be return~d exactly like the dollar coin and the quarters. Finally, ~U 11 updates pointer CONTYP to point to nickels and checks the contents of the nickel buffer FENIC. Since this is also zero, MPU 11 has completed the full-escrow payback of the customer's credit and it exits the interrupt to return to the standby loop.
It should be noted that control circuit 7 will return the customer's credit in the full-escrow mode not only when he presses the coin return switch but also when he deposits money in vendor 1 when free-vend switch 199 is in its "on" position, i.e., closed.
In its standby loop, MPU 11 continuously refreshes displays l5a and 15b. However, display 15b is normally not lit since its associated inverters lack a ground connection.
And display 15a will no-t be lit if there is no customer credit in vendor 1, i.e., the accumulated customer credit is $0.00, since all leading zéros are blanked. When the serviceman approaches vendor 1 to, for example, record the ~25 total accumulated sales figure, both displays will typically be dark. To read the accumulated sales figure the service-man inserts key 203 (Fig. 30) into slot 204. This results in line ~107 going Low, as described above, to provide a 9~g ground for inverters 53-58 (Fig. 15) and display 15b lights up displaying the total accumulated sales figure, i.e., "12.50".
To reset the total accumulatecl sales figure to zero, the serviceman closes switch 213 (Fig. 30), causing -the output of gate 215, which is connected through pin i of plug P2 to the CBl interrupt input of chip PIAl, to go High. This causes the IRQB output pin of chip PIAl to go Low, thereby supplying an interrupt signal to MPU 11, and causes bit 7 of PIAlBC to go High. MPU 11 identifies the interrupt as a clear total sales interrup-t by checking bit 7 of PIAlBC to se~ i~ it is Migh. After determining that bit 7 is indeed ~ligh, MPU 11 jumps to su~routi.ne CLRIN~, the clearing total sales subroutine. In subroutine CLRINV, MPU 11 erases the data stored in addresses lD and lE of chip EAROMl just as it did in updating the total accumulated sales figure and then writes the data 0000 into both loca-tions, again just as it did in updating the figures. That is, MPU 11 is responsive to the closure of switch 213 and the resulting reset signal to change the total sales figure stored in memory 9 to zero. MPU 11 then j~s to subroutine RDTOSL, discussed above, to read the new data stored at locations lD and lE. If the total accumulated sales figure has been successfully cleared, display 15b will now be blank, since all of the digits of the total accumulated sales figure will be zero.
. ~hile servicing vendor 1, the serviceman may empty any one of the coin tubes by pr~ssing and holding its associated ~3~919 switch, causing a High to appear on one of lines L95, L97, L99 or L101 (Fig. 27)~ which lines are associated with the nickel, dime, quarter and dollar change tubes respectively. A High on any of these lines causes the output of NOR gate G27 to go Low and, therefore, the output of inverter 1~1 to go High. This High is supplied through pin 1 of plug Pl to the CAl interrupt inp~t of chip PIA6, causing the IRQA output of chip PIA6 to go Low and bit 7 of PIA6AC to go High. In response to the Low IRQA output, MPU 11 initiates its interrupt sequence. ;
It identifies the interrupt by testing bit 7 of PIA6AC
and branches to the automatic coin tube em~ying ~ubrcu-tine PAYOUT. There MP~ 11 determines which coin ~ube to empty by reading PIA6A. Peripheral data lines PA4-PA7 of chip PIA6 are connected through pins 46-49 of plug Pl to ~e L95, L97, L99 and L101 (Fig. 27), respectively. -~
~'~, ',~. .
When one of these lines of circuit 179, line L95 for example, is High its associated peripheral data line, line PA4, will also be High.
Assuming the serviceman wants to empty the dime change tube~ when he presses the switch to do that~
line L97 and peripheral data line PA5 of chip PIA6 go Hiyh. Line PA5 will stay High as long as the serviceman keeps the switch closed. MPU 11 first checks line PA7 of chip PIA6 and then line PA6 but finds them both Low.
Next MPU 11 checks line PA5 and upon detecting that it is High branches to the coin return subroutine described before. Briefly, MPU 11 ejects a coin from the change 1l9 ~ ~

tubes, in this case a dime, by causing that tube's associated peripheral data line of chip PIA~, in this case line PBl, to go High. After ejecting one coin MPU 11 rec:hecks PIA6A to see if any peripheral data lines thereof are still High, which would indicate that the serviceman is still-keeping one of the change tube switches closed.
If so, it jumps back to subroutine PAYOUT and repeats the above steps. As a result, the coin changer keeps emptying the dime change tube until the serviceman releases the dime tube switch. Emptying the dollar, quarter and nickel tubes takes place in exactly the same way. After emptying the selected tube, MPU 11 returns to its standby loop.
To check or change the prices of items 3, the serviceman opens vendor 1 and switches switch 98 (Fi.gs. 17 and 38-40) to the price-setting position, by removing the price-setting module from holder 339, causing one input of NOR gate G23 to go Low while one input to gate G21 goes High. To check the price of any item, the serviceman~
then presses its selection switch 13. Closure of any one of switches 13a-13i (Fig. 16), as explained above, causes the output of NOR gate Gl9 to go Low. This Low is supplied on line L69 and throuyh yate 95 -to the other input of NOR gate G23, causing its output to go High. This High is supplied through pin 50 o plug P2 to the CB2 inter-rupt input of chip PIA4 causing the IRQB output of chip PIA4 to go Low and bit 6 of PIA4BC to go High. In response to the Low IRQB signal, MPU 11 starts the interrupt subroutine INTERP .

.

19 . ,~ ~

In subroutine INTERP, MPU 11 identifies the interrupt as a price interrupt by checking bit 6 of PIA4BC
and branches to the price display subroutine PRIDIS. In PRIDIS MPU 11 determines which selection switch 13 was closed by stroblng lines PA0-PA7 of chip PIA4 and reading lines PB0 PB5 thereof exactly as described above in con-nection with the selectlon of item 3i. When MPU 11 has found the closed selection switch 3, it stores the row information in buffer SELINF and the column information in ,~ .
buffer SELINF+l. For example, if the serviceman has pressed selection switch 13g, buffer SELI~F will equal 02 and huffer SELINF-~1 will equal 01. Having determined which switch was closed, MPU 11 jumps to subroutine LDPRI where it inds the position number of the closed switch in the same way as it did when itém 3i was selected for vending. The position number of item 3g is 07. MPU 11 then reads the contents of location 07, i.e., the price of item 3g, in EAROMl by using PIAs PIAl and PIA6 as described above in connection with reading the price of item 3i. Thusj MPU 11 is responsive to the actuation of one selection switch 13 and to the apparatus being in the price-setting mode to retrieve from memory 9 the price of the item 3 correspond-ing to that selection switch. This price, e.g., $2.90, is stored by MPU 11 in buffers KEYBDl and XE~Bl+l. MPU 11 25then returns from the interrupt to the standby loop. ~ ;
Once in the DISPLY subroutine of the standby loop, MPU 11 chocks line PB1 of chip PIA~ to see if mode-setting . .

."~ ~ ' ' '" ' '. " '.

~L~30~i9 switch 98 (Fig. 17) is in the vend position or in the price-setting position. Line PBl is connec-ted through pin 23 of plug P2 to the output of gate 97. If switch 98 is in the price-setting posi~tion, the output of gate 97 is High. MPU 11 is responsive to this High, , and thus to switch 98 being in the price-setting position, to supply the BCD coded signal corresponding to the price of item 3g to display 15a. Specifically A MPU 11 stores the prlce of item 3g in BCD coded form in ~Y
buff~rs DISP2 and DISP2+1. As MPU 11 executes the E~s~æ~
subroutine, sequentially supplying the values of the di~its of displays 15b and 15a to decoder 47 and actlvatin~, or attempting to activate, the correspondin~ units of the displays, it reaches the point where it supplies the data ~s~x~
in bufers DISP2 and ~P~ while sequentially activating the units of display 15a. Since the price to be displayed is 02.90 the MSD will be blanked. Specifically it supplies the data "F" to decoder 47 while activating the ~SD of dls-play 15a. This, of course, blanks the MSD of that dispIay.
Then it supplies the next four bits of buffer DISP2, i.e., "2" to decoder 47, which decoder constitutes means for decoding the BCD coded price signal from MPU 11, while acti-vating the next most significant digit of display 15a. As a result, the numeral ~2~' is displayed on the second digit from the bottom of display 15a. Next,MPU 11 displays the highest eight bits of buffer DISP2+1~ i.e., "9", in the next to last digit OL display 15a and finally it displays the last four bits, i.e., "0", of buEfer DISP2+1 in the LSD of dis-play 15a. Thus, display circuit 15 is responsive to the - ' .

~L3~
.
:.
BCD coded price signal from MPU 11 to display the price of item 3g. It is apparent that except for the contents o buffers DISP2 and DISP2-~1, the displaying o the digits of a price when mode-setting switch 98 is in its price-setting position is accomplished in basically the same way that the digits of the customer's credit are displayed when switch 98 is in its vending position. It is also apparent that the price of any item 3, not just item 3g, can be displayed by the serviceman simply putting switch 98 in the price-setting mode and pressing the corresponding selection switch.
If the serviceman wants to chan~e the price of any item 3, he uses one o the three price-settin~ modules, 337, 351 or 355, which constitute means for supplying to MPU 11 a control input signal representing a potential new price. Using module 337 as an example, the swltches 60-68 and 70 are used to enter a potential new price, switch 71 causes display 15a to be cleared, and switch 69 causes the potential new price to be loaded into memory 9. To clear display 15a of the price, i.e., $2.90, displayed thereon, the serviceman presses switch 71. This generates an inter-rupt since it causes the output of gate Gl9 ~Fig. 16) to go Low and, therefore, the output of gate G23 to go High.
Just as when the serviceman pushed selection switch 13g, ~5 MPU 11 identifies the interrupt as a price display inter-rupt and, after disabling interrupts from PIA4B, PIAlB, PIA6B and PIA6A, jumps to subroutine PR~DIS where it deter-mines that switch 71 was the closed switch. This information -.' '' .

:
~L~3~)919 : ~ ~

is stored in buffers SELINF and SELINF+l as SELINF = 80 and SELINF+l = 04 since switch 71 is in the eighth row from the top and third column from the left of switch matrix 76. MPU ll then determines the position number of the closed switch in exactly the same way it deter-mined the position numbers of the selection switches 13 and stores it in one of its accumulators. However, the position numbers of the price-settin-g switches, i.e., switches 60-71, are not the position numbers they would have if one simply counted the selection switches and then continued to count the price~setting switches. The posi-tion number of switch 60 is 1, not 25 (decimal) for example.
The price-setting switches are given their own position numbers so that their position number can equal their value.
E'or example, the position number of switch 60, the "1" key A on module 337~ is "l". This system fails for switches 69, 70 and 71 however. In subroutine SEL44, MPU ll treats these switches separately. ~or example, the position number of switch 71, the display clearing switch, is OC. When MPU ll ~-inds that its accumulator contains the position number OC
- it loads the data OO into buffers KEYBDl and KEYBDl~l and exits the interrupt. Back in subroutine DISPLY, the con- ~ -tents o these buffers, i.e., 00, are transferred to buf-fers DISP2 and DISP2+1, the buffers that contain the four digits which are displayed on display 15a. Since leading zeros are blanked display 15a is cleared. Thus, pressing switch 71 results in the clearing of display 15a.

lQ~

9:1~

The serviceman now uses switches 60-68 and 70 to supply a potential new price to MPU 11. To supply the new price $3.05 to MPU ll, the serviceman presses swltches 62, 70 and 64 in that order. Each switah closure generates an interrupt in which l~PU ll finds the position number of the switch an~ stores its value in the buffers KEYBDl and KEYBDl+l. When switch 62 is pressed,-MPU 11 stores its position number, i.e., "3" in the lowest four bits of buf-fer KEYsDl~l. When switch 70 is pressed, MPU ll finds that its position number is OB and in response clears its accumulator where the position number is stored. The lowest four bits of that accumulator, which are not "0000" ~binary) are stored in the lowest four bits of buffer KEYBDl-~l while "0011" (binary) the former value of the lowest four bits of that buffer are shifted to be the highest four bits~ When switch 64 is pressed, MPU ll stores the lowest four bits of its position number, which are "0101" as the lowes~
four bits of buffer KEYBDl+l, while shifting "0000" to the highest four bits of that buffer and shifting "0011" to the lowest four hits of buffer KEYBDl. Ater the closure of each switch and before the closure of the next one, MPU 11 has suEficient time to exit the interrupt, return to subroutine DISPLY and display the associated numeral. --That is, MPU 11 is responsive to the actuation of the key for each switch ~62, 70 and 64) to cause display 15a to display the numeral associated with that key. Thus, after switch 62 is closed, MPU 11 exits to subroutine DISPLY

110 ' where it transfers the contents of buffer KEYBDl ~"00") and KEYBDl-~l ("03") to buffers DISP2 and DISP2+1. As MPU 11 executes the DISPLY subroutine, it therefore causes display 15a to display the numeral .03. ~ikewise, after switch 70 is closed, MPU 11 causes display 15a to display the numerals .30 and after switch 64 is closed it causes the display of numerals 3.05. That is, MPU 11 is respon-sive to a series of switch key actuations to cause display 15a to simultaneously, i.e., at the same time as far as the human eye can tell, display the series of numerals associated with the particular series of switch keys that were actuated. More yenerally, MPU 11 is responsive to mode-setting switch 98 being in the price-settiny posi-tion and to a potential new price input signal, i.e., 3.05, to supply a coded signal (0011 0000 0101) to display cir-cuit 15. And display circuit 15 is responsive to the BCD
coded potential new price signal to display that potential new price on display lSa.
The serviceman can change the price of any par-~ -ticular item 3 to the potential new price shown on display 15a simply by pressing switch 69 and then pressing the appropriate selection switch 13. Switch 69 constitutes means for putting control circuit 7 in a price loading mode.
In the interrupt sequence generated by the pressing of switch 69, MPU 11 identifies the switch as the load-price switch and sets status flag FLG5 = 80 to put MPU 11 in the price-loading mode. The serviceman then pushes the selec-tion switch, e.g., switch 13g, corresponding to the item 9~g he wants to have a price of $3.05. This generates an interrupt as before, but this time, because sta-tus flag F~G5 = 80, MPU 11 does not re-trieve the price o item 3g from chip EAROMl but rather writes the potential new price ($3.05) into location 07 in chip EAROMl. Speci~-ically, MPU 11 identifies the closed switch as a selec-tion switch and then, in subroutine LDPR06, checks status flag FLG5. If this flag equals 80, MPU 11 branches to the price-setting branch of the program; iE not, it branches to the price-retrieving branch. Since FLG5 = 80, MoeU 11 branches to the price-setting part of the proyram. The Eirst step in price-setting ater checking status flag FLG5 i5 to clear that status Elag, i.e., remove the data 80.

This is to ensure -that the potential new price displayed by display 15a is loaded into the memory location associated with only one item. Otherwise, the serviceman could acci-dentally load the potential new price into several memory locations in an attempt merely to check the prices of the items associated with those memory locations.
After resetting status flag FLG5, ~PU 11 jumps to subroutine LDPR07 where it erases the old price stored in address 07 in chip EAROMl and writes the potential new price therein. This erasing and writing step proceeds exactly in the same way as in the erasing and writing of the total accumulated sales figure in chip EAROMl, described above. MPU 11 then reads the location in chip EAROMl where it stored the new price, i.e., loca-tion 07, and stores this ~3~

information in buffers KEYBDl and KEYBl+l. This informa-tion is then displayed the ne~t time MPU 11 goes through the display subroutine DISPLY. To ensure tha-t he has se-t the price of item 3g to $3.05, the serviceman either presses -5 switch 71, to clear display~15a, and then presses switch 13g, to retrieve the price of item 3g from chip EAROMl, or he presses a different item switch 13 and then comes back ;
to press switch 13g. It is desirable to perform this check since after pressing the load-price switch, switch 69, the serviceman may have inadvertently pressed the wrong se-lection switch, e.g., switch 13h. With the interrogation feature of the present invention, the serviceman can easily detect such incorrect price settings.
Typically, the serviceman goes down the rows o selection switches 13 checking the prices of items 3 and changing, by means of switches 60-71, those prices that need to be changed. Su~pose the price for item 3b were set to $F.35. Since MPU 11 supplies the data "F" to de-coder 47 to blank displays 15a and 15b one would expect that when selection switch 13b was pushed display 15a would display ".35". However, display subroutine DISPLY checks for literals, i.e., characters A-~, and if one is detected, changes the contents of that digit to "A". Displays 15a and 15b display a signal "A" as a ~ ~11, so when the serviceman checks the price of item 3b display 15a will display "~.35".
When he sees the character "~" displayed, the serviceman knows he must reset the price for that item.
Of course, the serviceman can use module 351 or 355 instead of module 337 to have display 15a display a ~13~9~9 potential new price. Using module 355, for example, the serviceman merely turns control knob 359 until pointer 361 points to the desired price on dial 357, presses load switch 69 and the selec-tion swi-tch of the desired item.
The method of displaying potential new prices with module 351 (Fig. 3) is somewhat ~ifferent from that set out above. Instead of switches 60-68 and 70, module 351 uses rocker switch 353 to set prices. Briefly, the serviceman opens and closes switches 73, 74 and 75 by moving rocker switch 353. Switches 73, 74 and 75 con-stitute means for supplying a price incrementing control input to MPU 11 to which MPU 11 is responsive to increment the price shown on display 15a. Specifically, switch 73 constitutes means for incrementiny the displayed price up, swi~ch 74 constitutes means Eor incrementing the displayed price down (i.e., decrementing the displayed price), and switch 75 constitutes rapid incrementing enabling means for supplying a con'crol input signal to MPU 11 to cause it to increment the price displayed on dlsplay 15a at a rapid rate. For example, if the serviceman wants to change the price of item 3g from $2.90 to $3.05, as in the previous ex-ample, he need only press selection switch 3g, causing the old price of $2.90 to be displayed, and then move rocker switch 353 one position toward the word "UP", thereby closing switch 73. Closing switch 73 generates an interrupt and MPU 11 in response jumps to subroutine INTERP where it identifies the interrupt as a price interrupt and jumps to ;
subroutine PRIDIS. There,it stores the row and column ' -1~0~

information of the closed switch in buffers SELINF and SELINF+l, i.e., SELINF = 80 and SELINF+l = 10, and jumps - to subroutine LDPRI. MPU llls first step in subroutine LDPRI is to see if buffer SELINF = 80 and buffer SELINF+l = 10. Since they do, MPU 11 immediately begins to incre-ment display 15a by a nickel. It does this by adding the data 05 to buffer KEYBDl+l, making KEYBDl~l = 95, and then branching to a delay subroutine DELA2~ In subroutine DELA2, MPU 11 branches to subroutine DISPLY to display the incremented price, i.e., $2.95, and then returns to sub-routine DELA2. MPU 11 loops through subroutine D~LA2 sixty-four times, which gives the serviceman enough time to open switch 73 if the desired potential price is dis-played on display 15a. After the sixty-fourth loop through subroutine DELA2, MPU 11 returns from that subroutine. It then strobes PIA4A and reads PIA4B to see if switch 73 is still closed. If it is, MPU 11 adds 05 to KEYBD1+1 again and branches back to subroutine DE~A2. It should be noted that adding the data 05 to buffer KEYBDl-~l ~ ~i~ the con-tents oE buffer KEYBDl to become 03 and the contents ofbuffer KEYBDl~l to become 00, since the addition is being done in BCD form and KEYBDl and KEYBDl+l are treated in the program as one sixteen bit-long buffer. In subroutine DE~A2, MPU 11 then causes 3.00 to be displayed on display 15a. After another sixty-four times through subroutine DE~A2, MPU 11 again checks to see if switch 73 is still closed. It is, so it updates the display by another nickel.
At this point, the serviceman sees the desired price dis-played so he moves rocker switch 353 back to its off position, opening switch 73. When ~U 11 returns ~rom subroutine DEL~2, it finds that switch 73 is open and stops increment-in~ display 15a. Thus, MPU 11 is responsive to switch 73 being in its activated state, i.e., closed, to continuously increment the price on display 15a and is responsive to switch 73 being in its deactivated state, i.e., closed, to cease incrementiny the displayed price. To load the poten-tial new price shown on display 15a, the serviceman merely presses load button 69 and the desired selection switch 13g, as before.
Moving rocker switch 353 one position "DOWN"
causes switch 74 t~ close and the price displayed on display 15a to be decremented. MPU 11, in response to the interrupt generated by the closure of switch 74, stores the row infor-mation, i.e., 80, and the column information, i.e., 20, ofswitch 74 in buffers SELINF and SELINF-~l and jumps to sub-routine LDPRI. The second step in subroutine LDPRI is to check for these contents of buffers SELINF and SELINF+l.
When MPU 11 determines that the contents of SELINF and SELINF~l are ao20, it decrements the price displayed on display 15a by a nickel by subtracting the data 05 from the contents of buffer KEYBDl+l. After this subtraction, MPU 11 proceeds to subroutine DELA2 where it displays the new potential price during sixty-four executions of the subroutine. MPU 11 then returns from subroutine DELA2 and checks to see if switch 74 is still closed. If it is, it again decrements the contents of buffer KEYBDl+l and returns .

to subroutine DELA2. Only when switch 74 is opened does ¦ -MPU ll stop decrementing display 15a. That is, as long as switch 74 is closed MPU ll con-tinuous:Ly decrements the price displayed on display 15a. Whenthe desired price is .
reached, the serviceman moves rocker switch 353 to its off position and loads-the price as above~
. Sometimes the serviceman may wish to increment or decrement the displayed price at a faster rate than that resulting from the closure of switches 73 and 74 above. To I .
increment at this faster rate, he presses rocker switch 353 to its full "UP" position (to increment up) or its full "DOWN" position (to decrement~ which in either case closes switch 75. Switch 75 is connected through pin 41 of plug Pl to line PB6 of chip PIA2, so when it is closed line PB6 goes High. ~U 11 checks line PB6 of chip PIA2 in subroutine I :
LDPRI. If that line is High, MPU ll changes the number of times it executes subroutine DELA2 at each price from sixty-four to ten. As a result display 15a is incremented about six times faster when switch 75 is closed than when it is open. I
. After checking ana setting the prices of items 3, 1.
the serviceman returns the price-setting module (module 337 351 and 355) to holder 339 which switches switch 98 to its vend position. Up until this point, switch 98 had been in 2:5 the price-setting mode and display 15a had been displaying the contents of buffers KEYBDl and KEYBDl+l. In response to switch 98 being put in the vend position, MPU ll erases (ln subroutine DISP72) the contents of buffers KEYBDl and .- , , 9i~

.
KEYBDl~l. As a result display 15a goes blank. Thus switch :
98 also constitutes means ~or causing MPU 11 to cease sup-plying a coded potential new price signal to display~circuit 47 when control circuit 7 is set from the price-setting mo~e .
to the vending mode.
The pin assignments for the major lntegrated cir-cuit chips used in control circuit 7 are as follows:

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In view oE -the above, it will be seen that the several ~b~eets of the invention are achieved and other : .. ,f~ -advantageous results attained.
As various changes could be made in the above methods and products without departing from the scope of ~;
thè invention, it is intended that all mat-ter contained ::
in the above description or shown in the accompanying -drawings shall be interpreted as illustrative and not in a limiting sense. ~.

'~

12~

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171 ~ 'H _ h~ ~ f~ .S_ 1~ Sf~ L f .~F~
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f ;~ f! ~ f~ ~F? f~L.~ r-- ~L
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1~ 1 . s. ~ ~ *
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I R ~h~E f~[~ ~ J~ F.. Eh~
cR c'h~ F ~" h -~T,'; IN~ L14 L71.4-:,R ~:`f~-5-- Lt~ IE H LL!H~ #~IE
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1il~4,t *
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L7 l ~ i l H ~tH~r~ r t f7. L r.'~1fl FL ~e~
h ~.-F 1~ rHE~
13~ `R~t~ t'~ L:ttl7 h f~ fl #~
4H ~f~ ;F ~h~.~3 E,'t~E ~tllNT~l~t` Tl1 E,'~'IT.
3 1 3 5~ ~ F`fl 'r'Et'fll . ~ NLl T L-:l7tlF~L E TE~
t TE~tr Fl~ f`~ H~ tClL:E FL~7.1~ FL1J~=$~
~135.~f7 _`Rr~ 1L7t1Tl3~' TEt~h7 ~/.:,.~;.i,'fl, Ri:~i t'4 L'4 h I~Nr!R #3:~74 1-1l3.S?fl ~tfl~ `ct r',fl ~Hr.~3 ~tlE 1lL7tlT~-1s TL~ E,'~'IT.
3 i;tll~lT F;~'T'INIU~ R L:llIt1 C1l1T.
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t ~ *
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L~ ; f~llphRTE LlllIN-T'r'FE ~'EL-TDI?.
1~; l 3i;f;1-7. ~ hi-~ri I ic CLL, 13 l .~ h _'flf~F ~r~t Ltl35~, fl l~10~1T~4 LSf~ ~ ~ NT'r'F~
-il3t-,.? ~IlF~iflTE I~CIIN-','hL.llE,'I OIN-~LIFFE~ h~iP~E~
~71.~ R ~h~rl f,~ J~iÆ4R J~ C:L7NTI.,t~-*L~HEc~:; FCIF~ Etl~ F-OOIN f l/FFEF~
Ctl. ,rlf1 .~-h,~ F~ht.~ f'NE liLttTLl.-, TCI L-LtlTIlJIlE.
13 / 3 lrl: *E,` I T
1~ 1 s ,7 ~ *
" 4h ~'h7.1 t- ~L7 ~ hE:R ~ R i10NT~:t,-r TO E,';IT.
lr.~i ~NÆ11 rClIIll FCIllN[`J. SRs,'E l~ UFFEF RC~ E55.
Cil.-~ ,R _h7:-: [.~F 't~ R liCINT~15 ~T,$ TE~1F_ ET ~ IN ','hLLlE
~l 3.~,~:h .-hl h Ç.iE .~i4 R LP ~ TEllF~I
~tl.~ *I`!ETEI~i1INE IF l'~E[.~IT.'~r:~l-N.
h . hl l. EE ~ L~i$ ~1" ,';
3I J l R, ~7., E ISL`! ~ .5~? R J51~ SLIE:TS~
1 '~ 8 s PH;~ 7 ~ ;Thf'. T HtlCFC.;' t~ C S~'~TEtl. 31309i9 h~ 1 ~E: '~ 'Rt-7, firlI ~lEtNT~1t-13 l -~L~ -~ *Cf~E~I T~`l'OIN ~'t7.LI IE . SR~'E C~E~iI T .
~Sl .~.4h 'h.~:- r!f- ~ R ~T.'`,' TEtlF-~
'71.~:' . .tl~HEL`f~ FCIR f~ULL-ESCFt-~ Fh7.T'ElhOk; FLhl~ f-LG~;=$0~ ~.
L~t-,~ 7 R ~ hh fL
rt l3.~" t~ ~RL~ L-t~ h hNPh7 #~--t~
~-S~ t-5 ,-h.:? ~ t-7h7C E.NE tll-NT~L~ Tl-t CQNTINI/E
L-;I-L~? *NnT IN F~ll L-E-,C~
rS~ *017PlPRf~E P~E'ENT CIlIN-~'RLllE h~ir~E~ ~IITH
~71.-?1 ~ THhr ot ~l Ot IN'~;.
h ~!h:'E: E:~ I L7l ~ H L~!hh7. PIh_E:~
71~,'?~ '7. ~t7 'E ~E 54 h LP,~s TEtlPI
~i 1.-. ?4h _h'.lt-t ,-~ , ?FF h7. JtlP SI~L IN~' t71~ 7. .-h l- ~t~ t7~E: 6t~E tlltt~T~i~i TO OHECk~ It7-CENT-. .
~I ~Yh ~COIN FF.E~ENT I~ OItl.
L~ l tOHc~k~ F~ Et1FT'r' TLIc:E.
11l3~:h ih?S ~h7 ~1N~h #~
riI.-?qh _h?,~, 13 7hflC: I~NE PlnNTCiL7. TO O~iNTItJ!IE.
7 *~ E:i7IN TLlr-E I~ E~lf7T'r'. 1JET NENT L~7IN-~'hLUE.
171-1Eilh _H'.~ 7~7 l7L 7hfl~ E:F~h i1.17tJThf~
Li l ~ II1. ~ C . 171 iF'flF. E F F.. ESEN T l~:l-1 I N- ', 't7L L iE fiP~I- E -~ ~; liI TH
171 js7,t ~THhT 17F l~ L'ENI ~-.
1-;1~+l7 ih _'fl'1E: E~C: .-.5t-~4 h Pll7NT.55 L:P,';~,' .4/il/Ili'-+4 El 1 i/.i~it7 'h'?E ~'t. ~ 'hh~ ~:ilE ~ll:/NT'i:7 Tn l~:ONTINltE ~
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7h ;'~7.t~7 E't~ I L~ 7 fl L~ih~ F It7. ~h~
Lii~tE~ r-7 ~hh~: 174 i-ll h t;N~ih ~i-11 L714l1~t7 ~htt5 ~t~ E15 -thfli: i.Nr ti~7NT'i:~ T17 1'l7NTItl11E, !~ ~ 4 1 rl t l ~-l-/iEN T l :17 I N Tl lE;i-- I ~; E. ~1F TY .
L3 1~1 J .t i5ilLti J ti~ET ~iEil 1~EtIN ~.~'hLltE.
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t H ~i jt,h _flr71 r.E ~E: ~ i lltNT5,'7 L~ TEtlP~
;ii i 1, h ~fltiE ~.~F 4 I h ST,'~ E~JH+ t 1-; 1 ~ ;- t L.`~ELH~
Iil ~i i ?h ~:r7&i~l E[i ~7r~hL7 h .~h7 r!15PLY
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t :,ET I~-Pt~'r'Efl~ E FLhli~; FL~ 4 ~ .
h _flE:.~ ~t~ 1~4 h F't~l't'~ I Lr.~hh $~E14 7~.h7 _hE;.'i ElrJ .7t:1~1~ tfl J~;F.. ' ~EFL~
*r~ Ft~I~J 11LIT Ii'l ~'ENT~h.~.
r- ~s I T .
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_"~ .t E,'~'I T
i 4_ .-: ~ ENP Eli- Ph'r'ERL.f~ .
n _h:1~ E[~ 7r ~ ~LI~iT~ 7 h/~L~7 .sl1 *I~E:,ET IN-Fh'T'E:flC~ ;tl~rJE FLR1~.
1~l 14.-, l h ~7hE:rl :-~ FE h L~Rh #:~FE
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L114~',.-, tS~T ~h't'E:fl~'fi-G~tlPLETEL`J FLhG ~ FLGt-.=$~
I;f 4-.4h .7hL:~ c.t-~ .~L-l h L~Jl;h #~EIl 11; i.:,.';h ~hl:i E:~ -E17E l~t J:P SEFLlS;b 143~ t.1-:L Efll;~ E:l lFFEf~ .
hl-r 1'E ~ Lr.~.'; #~
43:7R7hL5fl [.~F .~4 R ~T,'~: TEt1F I
. s ~hGI5 ~F .~it h ~; T,'¢ TEtlF'~7 1 ~9 Fr;~ Li~ ~ThF~ T Hiil;F.'~ 1s~ ;TE~ 9i9 17;1 ~i _'h1 .E ~ir ~;;7 h7 T.'~' TE~lF.s kli41 *L'LER~ LLlIN Fh7T'E:hCf~ EL~T~
~N~4_h _fipll, F 111.7.~;.s flL7/ F.' C:L7~iT'r'F
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' -H - ~ 7r'~ T~ 7 F~` T~
~-!i 47~ t. 7~ 11L1TINE Lt~EP TL7 E~lEt?1JI~ E f~!IN f~ELhr~.
~-.!44~ *
1~4~n 'hL.i`. f~'H1~71~7 h l?LlJif~7~71 ~Ik7hh ~ 7.-hr!
_/i1h ,7hfil' C~ 1 h F11N~ ` 7;'hh Flh.7h7P
~ 7 ! 7' . ~1~7 .-~h7[if ~ T~
i7 j, ~ ~i 7 *
7ll~,k7c1LlTINE Ll'7EP TO ~E-ENEF~L7I~-E k7LlN ~ELh-'r', *
i~ 77 ~h'E~1 E:4 1 ~7i l~77 h7 k-'UNk704 f7.Nr!h ~Ih'~h i 7~'leh7 7hE..... 7~.;7 F. _'h7i'~: E:F'h F:UNk7~7_ i77 J 7; .~; ~
~,jj jl",el,.7, .i .i;EFI711TIl~f-' ll~E{i TO riI --hELE RN[~ I~LEhFINlu F~E'-,ENT
L7 1~ ~ t I~ TEr~k'UF' r~-, .
~i!4t-.17 h ._',7'-' . t. ~t~ h [jI~INT LPh7h #~
~31~ 'fl . f;~. E~7 1~ t'? h SThh Flhlfil h ~hEI-7. E~7 li7t 1 17. ~;Thh FIh2h~.
ril~t-~l~ _'h-'fj E:.- 1~71~ h ~;Thh FIfl El-t-~ 7i~~' E7 1~1 h ~;Thh Plh.-hL
Lil 4/:;r;h _~F~ E.~ ., f7 ~Tflh FIpr~pL
L7 1 4ti~f7 ~ 17F~; F,'7 1i7~ 17. S Thh PIh~ Ç
t-~ LE~ F~ESENT I~TE~PLIPT~
1114~:. ?n IflF~ E:~; ~h7 h ~S~ ÇLRINT
j3JY~ l3 .t~iIshE~LINl~ llF ~IEN~ LIE~T. Fl~-C:ENLO,7r~ FLhr~
~tl-i, I tl-~l~PIT F:EI:f3LLI h~ LEf31~-T~ITflL-'-IhLE~ iNTEF./~llFT~.
~314~_ *
1~14 ~ .~fl . f3Fi~ L~ t~ O t h [j I -. I N I L ~.~flh i~l4~7~h _I~E t7 l1'4 h SThh PIfl4EI
-11YI .~f1 _E~itl El~- 1 l1~1.- h ~T~?h F'Ih~C.
lil~ .h 'E:f14 E:, 1l1l1E h STflf3 FIfllE
i1/4,, fl .'E:I~, E'~- 11171 fl ~;Thh FIh~-.h~
~;141-L-.'fi ~'E;Oh . ~ T~
~11 y ,~'.i :~
~il4:~3 Y'-LlEIF:O!lTItlE 115E~ TO ~;ET fLI f~. .
14L~I *
il4:.-:_1fi ~;'E:1-lE: '?h ;~1 fl ~;EFLI31~; Ot;~flfi FL~
.71 4:~.~h -~ 7r! ~ SET~ ~;Thh FL13 ~;1 4:34fi _'f:~F' ~? FT~;
1~1 I y ;~
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14L;~ *
~il4: SH -'~ 4 ~I h 1;~'EfLIJ~.- hNr,~fl FL
~1 4f:~'h ~ L-i F5~ ~'EO[j E:Ffl .'-ET~
~14~0 f ~LIE:f~OUTIt~E Ll.~-E{,'~ T~ ~;ÆT fL
i-114?1 *
~14~ _'E:14 ~f 1~ h SEFLI7~ R'hh FLI~
fl f:~31r. ~ h --.ET~ ~;Tfifl FL~
L; 1 4~/4fi _ f l fL .~:? F' T~
t ~LlE:)~l7LlTrNE LI~EL`~ TO I~E'-.ET FL~
L7 14'.~, h ~E~I~ ?.~ .~_ h ~EFLI7~ hN~.~h FL 17 FfllGE~ '3 -, ~; ThF. T H~1~f ~i.. *M~ . r'~ TEJ1. :~L13(~9~ 9 Cil4~ ~'E!E: Ç~ F~ ~EI~; E.~ ET, ~tl4?q *
~ii5l-Et *
Ci1~13l *TIiiE-r'R~E-(:~LL1~ TEL' :l ~EI~7~ IN~ ELE~'RTr~ NTR
31~i~- *I.HE~-~ F~7F~ LIF-11-~E FLh~'FL
4tl -!r~lr~ fl Tt~. l rt L~iRR FLlu~
L7 i ~I l3~;h ~1 f l ~ ThE~
E1t-.R . E_E1 .-:4 4l~t t~ flN[it? #~4r1 C1lE-~C1, R ~E:7~ f l l ~ E-.`El~ TE~I3l~i T~ E~T r!~l~N-J~ FLhCi.
h,:~ *~lf -J1CIPE FLRIi I ~; ~ET.
t t .SI-1 ? *
lE1 *~'HFCI; FLtN-FELh~'-ENEFI~l~ Er.~ fLt~
h l ~ ~ I *~ ~L
l s I .~
R ~'E: '~ J, TE:~ 7 TEt~
~S ~ t R R~ R #~ 71 7 I-t ~ ;R . E; r! ~ _~7-~ E ~ 1E TE - ~ I T~7 7 E~; T FL ~ Tf. ~ 6L/tFFI~ .
SJt. ~
3;.~1~ *TE~T F~ W1-t7ELflr-r!E-ENEl~ ErJ FLFtd7~FL~ 117.i.
N . 1 1 ~:h7 _ E: r! ~? I ~ TE:~ I ~ TE:t?
~tl I ?t~ ~:E:~h ~74 ld P' h~r.iH7 #~
7fl -E;~.d .-t. ~4 _E,_ E:NE TE~ 1 TL7 TE~T Fdl~ TE.~: EllFFEk7 i r~ I t ~UN-FELR r -r.~E-E/lEf;~L7 I ~-t.~ FLI~ll 7 tJOT ~;ET .
IS ~
~it.~,r-- i&~EL~; F~7~ diJN-ttl t.~E FLh~J~FL~ 3 --i f ~; r ~ ~
I-t I .~ ih ~E. E 1 ~ TE f1 ~ i_t-,fi ~E: ~F -:; 1-1~ fl flNr.~t~ #$~t~
E~ t.~ ~E,~d E~E TE~ t ro ENEI~7l;~Æ ~IN I~ELRr.~3'~ E~ 17 i~ Elf;~ll TE~ ; Tl~ TE.~;T ~t. 1. ~TI~T~
*l~lt~ ELRr-rlE-~ElJEfil~I ~Et~ FLF717 I-, ~;ET.
t *
~?1~ TEST F~F. t.~ llN-~1/.?r.~E FLRG.
~; 1 5~ ; FL ~
~15.-,3h ~:E:35 i ;:~ T6C15 T&h ' 4 H ~'E:., ~-; :-. 4 1 ~ H~J~h # $1~
' PE:f ~; f'~W Tfl~ Tn TE~T FLl~ P~'r'ERI~l~-&LlLSE~
i.~rR . f,.:~R ~Ll E,-: _E:~4 E:J~h T~ T~l TE~;T F~ Ut~l-fiELR'r'.
C153, *
~i l .5.:.~ ~ TE ~ T ~ 5 Th TLI~; .
5.,?h ~'E~C fr~ ~4r5 1~ Jt~ JSf~ 11hC~TI~
~i/54l1h :'E:~F ~ R ~'E'4E ~:1'5 TE~l~lS T~ EI~lNTINILlE
;4 1 ~i1 54~ ~tl~rll~ 5 ThTUS I~ ~lC--~31 ~:1154 ~ .`k ~, 4 t ÇL E~ EL E ~ T~IF'- L'l~l'l TF'~L FLhl35 .
L~ ;4.~ _'E~ I Er., !~4E h TE~C 1,~ .J~R '~J'Et~r.~C:~
C154r; ~fLINTINllE
;4,~ ;t ~ET tl,'~'.-Nn-l~- FLhli¢FL~ 4~7 & 1 54:.~h ~E4~ .~;f~ 41~ h L~ h #$4 171 .~;4~ R _'~4r. E~., 6~1 4 H 3~ ~EFLC~
.511 ~E.~IT.
;51 h ~ ? ~ ~ 4 ~ .- B~:F E~ TE~
~1l55~ *~ STflTL/~ I~ IjC.
1 5~ . h~EC~ FL ~ ~ EL E~ ~H TCP . P~!3 .~ .
H, E.~E~ ~:E 11~11-1 H TEf 1~: LP.'~: #PIh~-~h~
;C,f~ E flç 1~ h L
~51 , Fh.l.,É ~-t~ TH~T HI11.-F.5.' t~ 'C .~'~TEt1. '~
~ jI c~ f;~ t ~ hNr.~H #$.~
0;.:~.5, H ;-'E~E~ ,'E'~I E'E~! TEL'/,~ TO tS,'C ~;TRTll- NO ~0. ,-; *
t[.~E-EN,~l,I,-E r.~ L7~ LEN{
r.l th .-'E;~;4 ,~ i~ r.~F h TE:C: I ~' L r~hh #~r~F
c. I h .~E.~;t, h4 11L~ lr.~R
~1.5~.~R . f5:~ 1 R ~iT
~tl~,e~
~-il.5~ C:HEE:~ FCIF sELE~'HTL7F'.PP .r!G
i~ I '"-.. 5i~ .'E5R Rr~ ~It 1:1 Lr!h~
1~ 15 -.t.h ~ . .-:4 4r~ R RNL`!~ #:~Ct hl~.l h _is.~E ~ Ei ~E~ ;E~? TE'/'lf TO ~ 'IT.
~; I .5t.. ~: *
Ctl 5c~q tti; C I~ ~CI.
7 j~ 1 *~ET ~r~llN-~ELl~ ENERI~.~EG FLI~ s FLI~
~1 j 5 ,- 'h _ E t~ h TE:O_~L1 L r!hR #
7 ~ ., *
~i.51 4fl _~r. E;~! .-i-:LfE H J~ .EFLI~t.
J 1 1 .~; f .5 3 !.~, e. i ENEF~'13I~ L f;~llN F~ELfl~'.
L71~,, h '~e,.~ :~o I i7 h L rlhH #~IL~
~ii.ll E.t7 _'i-:t~ E~P ~-h[.~ h J~ F.. LINF.~ll .j/,~,.''; .tr!E-61:1LiN~'INl3 PELh'T'.131 .~::,L1h_~:e,h 6r! ~'EP4 h J5~ rJEL~ I
6~ E-INITIf:lLI~7E "TE.'~::" hN~ ;C" ELIFFÆF'5.
17. :-E~ P ~4~; 17. J5f~ ~'ENPL7/~;
L71~i~4h ~'E"7L/ ~ L7~ ~ El,7e E~ fl TE~ TL7 TE~;T Fnfi' P~-7.~ -PLlL~E-;6~ *Fs!lN F ELh'r' I5 EllEF13 IZEP .
t uPrl~ Tt " TE L7 " EIL1FFÆP .
~rl .S~L LS~t7 ~E:, ~ 4'~; 3 h T~E_ l L[ihh T6~
~71~6~h ~ ID ~i~q.:, ENE T~ 3 Ti:l IlPr~J7TE ~TEL7" E~UFFEF~.
~il5yL-l ~"TE~I~'l 6UFFE1~ 1~; c.7ES;~17. TEL~ T F171;~
? 1 *f h'r'E'tl1.l~~PLlL.C;E-L7N FLhl~; FLI;~ =$L-l.ii~ - *
L~ ..fl ~:'f;~ t-~ 7 ~,1 h TFI::7~ L[.~RR FLI3f7 5 ~ E:, L--: LLl ~ L~l~ tlN~fl # ~_ rt; ~ ;h _~E:, h ~7f, ~1.S ~:~EL7'1 E'IIE TE~e,Tn LlPPt~rE Pt~'r'EI;'I
,- Pfl ~'E:hC.'I;-Pl lL SE-I~i FL h~ NI l T SE r .
L11~;'?, ~JE~T FOF~ Pfl'T'E7R~ '-PLlL~E-~FF FLh~FL~e~ 31.~.
L-i i .~Efl ~'E:I-C: 1,~ TE,f) t7 ,-'E. ,~ S~ 1~/ l h hN~/fl #~3 1 ; I ~;L-11 lh . 'E: .~F ~ ,~ L-1E ~ E::-:F L7E~-.! TE:r:~E T~ E.'~'I T .
111 t l11 ~ PR~E~RI'~; -FLI~SE-Ls,FF FLF1~; SET .
l r,l1,' ;UI7r.'~t7TE F'h-'Eh~; TI~lEf~.
31eE1 *
-'34fl 7E:.~s:l ~ ~"~i h TE:I'_'ts, L~hh Ph'r'E~I
J31e.1t.'1~i 'E:17,.~ C1h ~E:~F ElEl? TF~L'~L~ Tl~ E,~'IT.
~31l-l1h *
31el3, *Ph~'E'hL.~ TI~1EP N~T E~1Pr~.
~-sl~5~3:' .tLlFr}RTE TItt_P.
h ,. F:.~ 4h ~.~ECI~
1~ I hS I 13ff ~7E:L?~-. 4 ~ ; ~ h 5 Tfll? Ph ;'E'~ I
Jile l I ~TEST FCIP TI~1EP=L~.
ilhl~f _'E:.:.:? _'i~'E::~'F E'~IE TEO. ~ TO E.~sIT
L-11 t-~ PR'r'Eh~ TI~lEf;~
~l 52 PRL:iE L:1~';? '-, Th~T HtlCF~ *Jls'l' S'r'STEJl. 3L3L3~9:~
~ilt.~ ET ENr.~ 1F-Fhf'E~h~ EIIL~;E F-LI~llbi~'FLG, =~B4.~.
E:~n 6~ ~14 f1 L ~jRI~ #~l~t4 ~11 r, I ~ 1 E~ / 4 f~ .3~F' ~;EFL 1~, ~i 1 t. I, ~hL EflR Ff~E~ENT ItiTERRUFT .
Lilf.16 *E.'~'IT
~It.14fl ~E:~.F ~:t. IL-i4h R TE~6~ ~ Lr.~ FIR4R~
L~ -. }~P. ~E:qr' 3f~ F TI
i I t ' I ~ LIE[.~I~ TE " TE~I~ " 6LIFFER .
~il c,__l~ ~6q3 ~1~ T6~'3~ ~Et:~R
r E1.~4 ~ 3 1~ ~T~ TE~
~:;1 t. ~4 * TEST FOR TE~
;h ~ t _~t~ r~E E, t SNE T6L'~ TC/ TE~;T FOR PR'~61 FLlLsE-hl~ JltlE-Elfi~E-L~ ?cfi F11FFEF =~.
~It-~ CHEC~' ELE~'hT~ tlC1TLI~ ~PEEP ~;~sc~.
C~fl ~E:~S ~i. , 4 fl r~o3.~ L PflR Sf: EEP I
l t ~E ~R S 1 4P h l~tlPl:l #:~4P
.ItFf .-E:~1 _3 Oh _SflS 6L~; TEC3~; T1~ r.~E-ENEP1JI~E l?VN F~ELR'r'.
1t~ 1 *t10TLlR SPEEr.~ FL1L~E5,'~E~.
*C:I~E~ fL7F tiOT1-1~ SPEEP i / /~1 F11LSE~;!SE~ .
~I tr.-~311 r FI~E SI ~ fl TE,1~34 L't1Fh #:~c4 L-;1t.~.41q. ~'E:I~L-t _E L-t~ E:h,': E:ClT TE:f.-.~ Ta ~E-ENERl~I E F'11N F~ELfl'r'.
35 , *EI Es~'hT~ PEE~ I5 WlTtlIN LltiIT~;.. f?E-INIThLl~E ~ L
/ c~ s~ *ht~ri C:1~NTI~IE .
,.... , h ~!~:fi~i PP ;:~S4~ h JSR S'E~ t, l~lc.. ,:::h ~iE:fi5, E _E:~c,- fl JttP TE:L'',' TCI TEST FOR' PflyERl'~-FllL --E
L~ S ~ *r.~E-ENE~1J I;~E S~LIN I~EL1~'r' .
,4~1h ~-E.~S :~ Ef h T61:~sf~ L~ l #$1~F
1~1 t, 4 1 h ~E:hh' f:P ~RE~ h'JS~' PLI~Pl~
LS J r. 4 ~ ~PEE:~ N1'IN1~' [.~ELt~
131 r,4~,fl ~-~hr~ EtP ~ J~ lENr~
131 ~ *rlI5flE'LE LE~'EL Sl~l '~;, L~1r;4~ ?1 7F I~ h1'Lfi' P Ih.~R~' IS I r;4~ *L:LEfll~ Hl1P I ,~1:iNTflL ~nLENL I~.~S.
h ~E:E, .~ F 1~l35E 1~L-L P Hn~'~;L7L
4:-: *PISI~E,LE f1t~r~ 1~LERP RLL INTE~I~'L1P7-S.
1 f.4~h .~-'E:E.'~ E~'P sfiE~i fl JSR PISINT
r,~ RE--,ET R11~-F.'ELh~'-[:~E-ENEF~L11~Er~ FLfll~.~'FL
~,11 t,~ SET RUN-RELfl r~-PE-E~Efi'l~ EP FLfll~ ' FL1;~
~i l Ç~;.'.~'f1 s'E:E:~ .~ . PF fl LPRfl #:~[.~F
i.-,h :-'E;E:E: E:P sE'1~ h' JSR f~'Ef:L
;4h r'E:~E .'-:fi 1~1 h LPf1R #:?5:1i3 ;.'.'h~ 13l~ E.'P _'E~tE.' R JSR ~;FL1JÇ
lilr'.5r.H s-E:J~:. , E _'E:, Ç fl Jl~lP TE:1's~ TL7 TST FL7~ P~ PhL'~-FULSE-J~7 I r ~i 1 Ç.5~ ~ INTEPF'LIP T~ ~E~ 'I L'It *
*~'L7INS hNT~ flJj~PL7T ~ELfl~
,e, :~h ~E:L'e, ~1, h IN7Ei?,~ F,,P *I-t7" ~-t4, $~t~ 113 74~7.
fl s~ h 1~ ~'c'1.~ ~t31~
~ile,e,3 ~E:E~IN ~I~LL~N1i INTE~I~UFT~.
111 ~-.~h sE:L~ TEF.~ L.LL~
~iI r~1,5 ~-TEST FCIP "T~E~ ITE~F.'U~T
~IÇÇr.~ ~E~L~ c:e, 1~41 fl LPfl~ FIfl~flC
~;tÇÇ, ~ 'E ~Y F.'C1LR
~IÇ~,~h s~L-F ~'5 ÇL7 ,j. P FL~S TP~I TF ~-E~'IL7E INT.
~53 .. - .
.

r~ 173i7 '7 rh~T h'tl~`F~ M~'I. E~'r'~TEtl. ~L13091$~
r'.' ~ TE5T Fif;~ ~FEE~----.EN-,~7~-C:L~7C~
rilr~ fl '~'~1 F~. l~i?1'.~ h LPhl~ Flhlh i / t-. ~ I h _ E~ t ? F L7L h L1 I r" ~h ,~ ? RCIL J7, 11 ~ h, 1~7. : Erl~ c.~i ~;F _ C~
*~`HEl-l~' F~IF l'LlF~ F. EN~' r'. 'L ~7 IN ~ .
~-i l t-" r~ f~ ~ E [!L -'h FE h7 ~ P~h' # ~ E
, r, ~PELh7.'r' I h 7~ h ~ E;r!h7 E:r.~ ~ 'F.- t7. J'~F l.iEL h~
*l~Er ~l~IN:. s'EC T~
~ijr., ~.h _'i-PP Ft. IL1~1; H7 L~R6 FIh3~7.
Clli.,~:7 ~l'HEt'r~' FOF CL7IN~ Ollf~FEN~
*INITIhLI~E J7tlTI-Jfll-.l:;FclT-~iEL~ E,~'LlfFEF~; ~7.[i[iFE;;~, ~:31t,:~'h~ l'E 017sE~ t7. L~ #Jhl~F~
~-ilt-"5~ h ~E,E.. iF, ~ h sT,'~: Jh~F5 i l j t~ ~ * INI TIh7. L I.-. E ~!EL h~r~ oN -~ Tl~NT~ 's~'El~ TL7i? .
~i i t.,~.Sh ~'E~ E ~ 7. L~ INTEt 'i$- l ~ r h .. '-~E ~ [. F ~ ~1 h '. TN .JhEk~F 7 I ilt~ .tI,V I TIhLI~E C:17I~JS~ LiF~'~'EN~'~' ttfl5~;INI7 ~.'EC:T~F~.
t:~ h ~,'r-'Eh :'.~ I7L~' h Lr!flh #~t:~
h _ E:E E ~ 7 ~ ~ h7 --. Thh .~hE:~F:
~ / c, ?~3 t l'HE~';;' F~7;~ ~:1 E~1IN INTE~plJp T.
C1/t,Y/fl ~ E E.E /Cl/~ h LC~' #PIh;~EL' 7/~.~'f7 _E:f I .~r.~ 7E~ E El~f~ '-7IL~75 i / c, ~. . h.7 _ E:,~;. c 5 .~ E, E, i'. 5 I :l~ I /
/c-.4~ :t:/'HE~ r F17F~ ;~5 L'ENT INTE~pllpT~
~ I t~ h _'f'f5 E :E 1~ h LP.'~ ~PIfl.~E~L' L7 1~; -. r.h ~'EIF:~ c~ L-:~E E~;F? L'nI~i C,~ E,f~,7 ~ 'F .-'I.. :~El E.~
L71k~ I'HEl~h' F~7F.' 113 CENT INT.
Illk '*ll ~;~fC E:E 11l:~;~ R LP.'~ IR.
1-1 1 ,~L717h ~ F~F E r! /-, ~ . t, f EISP ~. CI I L~75 17 1~ / h ~:'C ~1 / C'.5 ~ ~L ~ 'P El'5 L'CII I
i~ / ~ 1-1;~ *E/-)El~kr FClf~ ~; EEt~/T It~T.
Ii/ 7l1:,R7 ~ :L-1.-. C:E /Ll~t:4 h Lr!;~; #PIh/hC
i7~, C!4h :~1'l7f. :,:[i c,~ L't-.E E:~P ~7nIC~5 i /, l 15f L ~; ~ 1 _1 1 ~ E:1,5 1 ~7~ 1 i7 i ~L~t~ ~I'HE~ ' Fhf~ ~!hL It'!flTL ~ INT.
I~/lf~1~h .-C:hfl E:t' /h/ / f~ L[.~h7fl PIf,~h7.C
~3 / ,~ 7, ~I'L~7L`! 4 ? ~17Lf7, 'C:hE ~5 ~.3 ~L.43 E'l'~; ~'flL Ir~ I
hl, lh 7;1l17 C~ 'C~ k.ENI''T' INr~i. FhU~fP.
L-il, l lfl ~'I'lL~1 E:~ IL143 h LPhfl FIfl4E.'C,' h I f~ .'C: I 3 4 ? F'L7L fl 71f 13 ~L'HE&h fCIl? h ~FLEI~TIl7hl, L71, 14f7. ~L'14 5 I~ ~13~E Cl':~ ~;f~L
~i l f I .'~h ~ E: 1 c. i 4 F'nLfl L-l 1 ,~ l t. ~ I'HEl'f r FhF;~ I~FL h f' Ft? IC f .
Ci I ~ L7 c I . /, c ~i / Lc ~ &~.. ¦ E: I .~; P P IP
L71, /:-:h _I'f ~ F~t. I /C~ LPflfl PIfltE'C
ii~ f-I ?r7, .~1'/1'. ~ FClLh7 7/f ~L7 kl'HEI'~ Fi~P l,/?EPIT J~EChLL.
1~/ f-_'lh ~ '!5 ~ ',,4 ~ F~EI.C~' h1f-~ tl~HEl'h Fi~ LEhPINl3 TCIThL '~hLE~; INTEF'~LIPT.
fl _'I'IF E.~ /Lll-lE h L~.~hfl F'Ih/E:C ~17L fl ~/ f-~-~h .'1 ,'~ lt. ~L~ 7. E~ TE~
~tlf-~'5h ;~1'.'~'4 E:~. 1 lhl h L[.~lhh FIfl6~7,C
i3 / f~ h ~ 4 ? FL Lh Y

F'HI.- ~l.sI '=IHI~'~ T H/1L-E~;L, :t:t~ 'O ~ TEJ1.
', *L'HEo~ FOF.' I:iLlTEl~7fl TI O F19~'OLlT .
L-1 l, . . ~fl ~71~ ?~ F .'C~4 ? E:O c ~h 'r'UI l T' H ~ f'flL SE I N TE~'F.'UF T .
sL~IH '1'. '~ ' ItlTE~ TI
~ j I _ _ I .y 17l ~ ~.. s *F'HTOH
fl 7o~r-~ , E .-OF~s R OL~I l Jt1F ~'l IL1~S
~il, .~.',~1 _l ~E , E ~ r!7t h SE~L Jt1F ~;EL I
, .st.~ O.s I , E ~r~7~ h F'k'l~.~ JtiF Ff?l~
~1---11 _'1`-~ ~ E ~'I'Er! H k'El'B J~1F' k'EOl~L
i~,.s:~H ~ E .-l-t.'~O h ~-.O~tl Jt1P 5'~01~
~ii, .-. .~h ~1: .h ~ E 'h.~07 fl INTEk.~ J~ :LFIN'~' H ~'I-:~s[.~ , E ~ L~T~:~'l Jt7f TE~L-I~
Bl, 4Ih .-041~ ~l NOF
01, ~ L.~ 71 NOF' Lil, ~ fl _'l-~; ' L1 1 NElP
't t $ 'flL I L`!H Tl7P INTEk'lr.'llP T SEPs,JI l~ ItJli .
~71t~ IL~h~'LE INrE~F'LlPTS hN~.~ tiEEii111tl1~E-~!ELh'T'.
l, 4f.h ~-744~ t'~ I'E.- 1~ I,'hL I~ I J~F. IN~
h ~ 4~ ;t-L~h l~lP l'l'lNT~
4;' ;~Ph 'r'L7LlT '-.EP~'IOINli .
1,1, 4qh _~1.4? E:~ 'I'E.~ h f'hf'OLlT J~ IN~
~,-11, 1~1~1~'.EN'-.E Ol'~IN Tr'F'E FnFl F7RIT~dUT.
;Jh ~ 1' I-E ~-'5~ h ~I~'r'llLll L~ #I.I~IN'~-_'h ~'C,4F i,~.~F .54 h ~;T,'i TEt1PI
131~ 7. _'I'.~il dE L1l~4E h L~,'-`i' ~FECINE~
417.~4~ -L'~;~ f,~ 11170 fl L~h7h FIflf;h~
h ,~ ~ Cll C:L C
L71 ~;t-~ .?~ PR'r'dLI~ R~;Lh 17~ -'h ~ ? ~ f;3 E,L'S FR'r'ClLI~
LIP~:~h TE ~ 'EC TOI~
41 l~ ;p ~P ~'~iE4 1~ .JSF.. ' ~ NTOC
41 I ~h ~E.'~iE ~t-~ F:~ .-L'5.; ~3NE.' pflf'OII~
t~ l ~ E,`~ I T
171rr:~h l_'L'~17 ~E _~ 7. Jtlp LPF'f?lL~
L'11 ,~r;3 ~f'h~'C111T L:l7IN.
171 1~64fl ~ 6- ~C lL7 h F'fl~'C1LI;~ INC
C;l . 6.~h _'C~ E ~;4 P. LP,~' TEtlPI
L11 ,~;6fl ~'L't-~7 EE E1El h Lr.~.'; El., .'~' Ll/ 7t6~h 'Ct-~/ Pf 41 fl ST,'~, L7fiEpH~
Ol, r.:~7, ~06f, 7E _'6flf' h7. JtlR REL'f/L~
6~h ~'&r~ 5 ~'~E,'i' 417,-1-lh ~Ct~F h6 Eil h LPflPt IJr~
1 fl _'C ~ I PF ~ ~ ~ fl ~ T,'~' Jl7. ~
11~ .'h ~ L' E11~1 1-7. INC Jhl~'P5~1 417~ h .-'C~6 ~ ElIl1~t6 17. P,~L JflCl;f'~
C11 ,~7~h ~C:- ~ PE f 4 h LrJ,I; Jfl-~'P~
i1. ~ L7l~E: C~:~ INN
~.l l 1 f-t.h7. ~:L'1-C: ~.~F 1 4 h ~;T,'~;' Jl7.~'f r Cil ~1~rfl _L', E riE ~- fl L~i.'; JhC~'P~
1l1 r r:-.~7, ~ 717 17~. L'LC
41, ,-~h ~~c,cI j~ fi'l7Lh i~ 1, ;-,'L7h ~C~ RT~
I.il 7-~:1 * *
7 1~ Y :.E~sJIC Ih'li INTFRfil-lp T~
,;i 1 7: .~. *
1,:?/r~4 t,~Ef~s'ILCf' "~fC " IN JEF~f~LIP~
'55 . ' .

FfllJE~ ~:t: ,- . TflF'T Ht1~`F~.~' *t1S'I~ - 'r"t TEt1. ~L3~39~9 I :.S .t r~ * TE ~- T F~7F~' UFi -r.~ t 1rlL`!E F L fllJ - ~' FL ri~ S ~ .
-. r *
L1l7~-s~ L'sB ?i ~1 H TE~ 11 LPflfl FLG~
~t/ ~h ~ 5 .:i 4c: h hl`1rfl ~ S
-jl Y~-t~ _t~C. ~ E'El~) TE:B~t~ TL-I Hfltlir.~LE hhlTI-~hL'l~POT ~.~EL
~; ~1 .t.IN ELE'.'fiT~F' r:rlt1Tt;~ L.
~t 1 7 ~ ~H ~r~ 7E ~ E` 1~ JiiF' TE-'i ' I L1 111, Y.s tLIFr.hTE i:rlIN~ s htl~I-Jfll~Fr1T PELh~
ril ~ifl _1~c~: Bc ~ii fl Tt:r~_' LPflE #~t~
; i I . .5 ~ 1~0 I N~ EL R ~' .
~?; .~R _~':'E L'E ~ 7rt~' R L~'~ #.~hBi;P1 ~ . 1 . .t r~ i 1 qS *l IFtLrtlflTE ~iELfl~ lFFEI~ .
~I, S7~H _1-~1 sr.~ r.~4 E:'--tF' TE:rL?7 i.-1 j.5~ i7 ~BHcL:.:-~ FO~ fi~1FFÆk' Æ~IF'T~
~'11,'~1~
Ji-?-~ :^'r~ Itr .'I ~r~ NE TBL'~?~ TC1 Bl~tlTIN!1E.
t.... *
~t~ ?~ ~ENhr-'l E s 1-L'I IN- INTEI~ 'UPT.
~S~ h' ~ S7S B~ ~1, h Lriflfl #~L?~
L7 I :~,-;H :~1~ ~.7, E~r 1111~ Tflh FIfi_'fi'L' t, - h _ ,~ 7,~ EL:~
~t I .~ ; *
TEST ~.5-BEtlT- ~.~FLfl~' rtl~l~, *
' 11 fl ~ ?E: 0~ TBÇL1.~' IN'~' .?l~t'l,_'h ~E~r: ~P 31; _'E~.~4 6~f~ TE,~C~37 ~1 :3t 4 tÇHEEI~ ~rlF' EltFFEFt Et1PTY.
1~ 1 3, 1 ~; *
3l:?E, ~ E rEÇI~ T~ t~r~llE TE~;T.
~l Sl 7 .y, I iI~1:3 ~E,'VFFER I~ EtlPTf'.
1~1:31 ~ iEN,L7,FLE ,'5;-1'ENT5 INrEF'r~LIF'T.
~11 ~-.'_"1 :t`
fi~ , h L~flf~ #~
~11 ,C:_'_R _'L'fi~ ' 6, I ~1~,, h STflfi PIfl~,6Ç
,'p.S .~iR PEI'E
~" ~
'-; I E:~.~i *EHEI-:~: EdF~ I r1-L-'ENJ5 PELf~
il:-:.-, fl _l~fl5 ~i~ TE,Ç~l4 IN,'`,' fl ~ I-h ,~ 6~R TE~
~11:-:3Ç ~TEST FL-If~ E~lPTY E~LIFFER.
_'I-:E I E,'NE TE,'I :ÇS
-ilS3. t6llFfEF ; E~lF-'T'r'.
Çt 334 tENFl6LE lÇ-l~ENT~; INTEF'F'UPT.
51:-:.:5h _15hE: ::~t- 11~ fl L~h .S~-.fl ~ Li E:~ 1~1.-'3 t~ ~Tfll~ PIfl5~1 I-i I ~:3 fl _ I~E:l1 51~ fiEI5E:
I-i I E:- . :3 ~ TE~; T . -ÇENT~; r!ELflY
~i l .3.:. ?~? _'l56 I h:3 TE~ 5 I NN
1:5;~llh ~'EE:-' :3P _'i~ f~ E.'~F~ T6çL1~
i TE~;T FI~P EMF T'r' f`UFFf f~: .

t *

~- ~

Ph1,E 1.~ r~T Htl-F51~ Y:.TEIl. ~113~9~9 sL.E:4 ~ -L-E E~NE TBLL16 7~' E.~IT.
~31.-,~ i *
t N ~:4 5 Y E:l IFFEF I ;; EMP T ~ .
t3 1 .. ~ o *
i~l.... 4, *E~hL2LE s-6ENT~ INTEI~I~UPT.
.74 .2 ~
h ~6t:t- 60 ~ ~ Lr~hfl #::~IL
3h Pl-E~ E, 1~313? ~ STflfl PIfllfl~
~il:,51fl rl-E:f: 5R ~JE6E~
t-11~.~; H ~6E:L- ~ L:LE ENE T~l 3t-, T~7 E.;IT.
*
~31:~5~ thLL hNTI-JflL-~pL~T ~.~ELhr:~ hF:E. EltFTr.
iS tFEE,ET h~TI-JhC~.P~lT ~.~Lh~ FLfl1~.
;t.
..5~ h . 1 E:E .'-'h, F t~ LL`!hfl #~ F
,fl jrl~l~i3 ErJ ~61~ fl. J ~ I~EFLL
~i I ,L:.~ ~ *
3l:7 k~-1 .t:rJ I.~flE~LE TEL~ TE~PL/PT~.
~i I .$o I *
~31~tc~ 3~ o ~34 1~ L rJhfl #:~3~
~31, t,.--,fl ~L~L:~i E:,-- I ~ ;TF~fl PlHj~hLr 31:~Ç~ ~
6~ *ENfi~LE flLL Il~TEf~ F T~;
~1 ¦ . h O :t:~ 1 I N~; .
tk~fl Pl-C~3 E.p ~ 4qc h J~;~t f`Cl~tT ~-t L7~ 1: ,'rt,$ *1~Tl-IEF~ INTEfitfitLlPT ~.
~;I,C:Ç~h _CL'E EC~ .~I~L~ ~7. ~F E:LICIT-C1l,-'r L7 t.l~LEf1l;? P~E~ENr INTEfitFLlpT~
I~IC~tf Ih 7C:L-:E 6ct 1~-t4Lt R rEL'I~t~ Lr.~hh FII-7~ 7.
l~t I 13~_t *EI`t'I T .
fiI~; t3 .~
ftlC;t~'~l-7 j"tl'r.'l ~E _tl-.;tfl R Jt~lP IllTEfit_t ~I, t~ Hi1F~
L71~2~ *'-.Llt7~f~ClLlTINE /1~;EP T~7 LlPPflTE hNT.I-Jfl~ ;P~7T.
I ,ctt~~~. *&ELh'r' EUfFEk7~; .
,s"~c~t .~
~/ .- l ~7h _/.~.i4 fli~ L-t fl T E:CIi~ L~.~flh ~t ".;
I-tl~$:;tL-1f~ f~.lÇ ~ Lt~ I.C~E ftEl;~ TftL'L72 L~ 1 7 ~ 1 fl s~/ f~ PE~'R
~-11 ,c,tr, ?fl ,: C:[.i ? R,~ L~1~;St fl ~;Tfll~ Lt~ ~`
~ l E::-:3R ~L [.~E: 3~9 TEI~L-13 FT~i L~1 I 3C~t~ *
~i l ~ c ~ * E~PEEf~-~;E1~150F l.-`L7LlNT LlF[.~flTE .
L7 1 ,:tt;~ttr; .~
-h7 i~l.r.~ & 111~4h -~;L.11~ IN 5PEEP1 t ~ *
fi l ~-c~t~ *I:LEh~7 INTEfi'F~tUPT.
~1 1 ,$:~17 I;l:.~lh ;I::PF k~ t R L~hR PIhl~7P
L-11:-:~7 ~ ~E,.~ I T
~s; I 3~4 ~h ~ ~:E~ ~,E: F:TI
~-1 1 ,s 94 *~ lt3L E INTEP~L1F TINC PI R 5 .
fjl~_t~; *
~l~t~Çh ,tl-E3 PP 'hFC ~ INPI~: J~;fi;t PI tINI
t~ ~
~1 1 CS ~t f~ELfl- .
~,S11 tt~7,.? *

~1 51~ pl ,?I~EÇ L-E L 1Lt ~i fl INPI3 LP,i #:t~L~t3~
~ 5 7 FhG' ~ Tfl~T Hll~-F~iS ~ '0 ~Y~TEJl. 3L3~D9~9 J ?~7, '~t~ [~ -~ 7. J5~ ~iELRf2 7iq~7'R 2~ 0 J? F~T5 ~-11'?~ *[~I~R~;LE OTHE:F~ INTER~L1PTIJI'~ P~fl~5 flN~ riEE:17L1hl1~E '-11 ~1 ?1t~ *
e,R .-rE~ E~! -flE~ EC:RL lsR ~I'.INT
_E:F~.l, E -~ H JJ1F' ~;EORL I
~7 I c ,~,~
? *ooIN--~ o~lRFENl'~l IIYTEF~F'UPT 5P'.JIOItl1~.
~1 ?1~1 *
r.~I S flE~L E. I NTEF'~UF'T FoLlN~i .
~1 ?1~ *
F, .'.~ 7 1'17I~7~ Lr~P~fl ~ 4 01 ~20F~ h7 ~ I k7 5 TflFI I "'~:
*
Y OLEh7.R I~TERR~/PT.
? 1 ~ F~ Rt, ~ L[~ 7 . ,~
? 1 ~ *
1 q t TE~T flNTI-Jh1.1;POT r.~EL17Y.
31'?2~3 *
L-,1'~ F~ riE , 1~1 t7. LP~ t7l31~P~
L7 1 q~OF~ ~7.~ 7~ t7 LP~7fl 13., .i' ~-ij .~r.--,H ~1 F~ ~- IF rijlF E:NE L:OI~
1 ~? ~ 4 :t.
t ~7.NTI -.J~ PL7` T E:LIFFE~ I ~; E1tPT~r' .
~31~?'~ *-,h7.','E C:ClIN-l~U~fi'E~1L 'r' Pt7.Th7.
.t:
~31 ~':31q 2C:FF r.~ t t7 hNPE~ Jfl!~
ff _~J~ 7 3tr; h 1:1F'hE~ C:C1IPEI~
171 ~3.. i7h ?~ p ,- 3~ 7 ~Thk ~.tlIf~EI~
. ,1 R ~ iF 13L F.. 'k 11~' ~ i,"-, .t INI TIt7L I~E ht~TI-JhC:l;PC~T ~ELt7'r'.
3 1 ~J~ .~
ti~ t7 _~.1C1~-. PF, ~-t h ~;T.'$ J~71-.l~p5 131~ t,h .~p~1:3 PE ,~ t7 L~ t7L.~7 ~i1 :'. ., ~7 ~: r!~-1t7 t1~ L1-1 ~7 L~jfl~7 ~,, $
~3 1~3:3~ 2PI~1' PE ~L-1 t7 Lrll~ Jt7L-~P5 11 :~.s~ L-1r- fl~ h ~Th~
~3 1 q~
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..

Claims (38)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Apparatus for controlling the functioning of a vendor for vending a plurality of items, each item having at least one parameter associated therewith, comprising:

a memory having a plurality of addresses for storing values of at least some of the parameters in predetermined memory addresses, the parameter values stored in the predetermined memory addresses being electrically alterable;

processing means responsive to a plurality of vendor status inputs,inputs, a plurality of inputs from the memory, and a plural-ity of control inputs, for performing arithmetic and logic operations with those inputs and with the values of the par-ameters associated with the items in a sequence controlled by a preselected set of instructions which constitute a pro-gram and for supplying output signals based upon results obtained from said operations to control functioning of the vendor, the predetermined memory adresses being accessible by the processing means and the parameter values stored therein being alterable by said processing means;

interrogation means operable by authorized personnel for re-trieving from memory the values of at least some of the par-ameters stored therein; and display means for visually displaying a parameter value re-trieved from memory by the interrogation means independent-ly of any other input of said processing means being equal in value to the value of the parameter retrieved from the memory, whereby authorized personnel may utilize the inter-rogation means to retrieve the value of a desired parameter from the memory.

2. Apparatus as set forth in claim 1 including means for supplying at least one input representative of a deposit of money in the vendor to the processing means, said processing means being responsive to said money deposit in-put to determine the amount of credit accumulated as a re-sult of said deposit and to display said amount of accumu-lated credit by means of the display means.

3. Apparatus as set forth in claim 2 wherein one of the parameters associated with each item is price and further including means for supplying a vendor status input indicating the selection of an item to the processing means, the processing means being responsive to said selection in-put signal to recall the value of the price parameter assoc-iated with that particular item from memory and, if there is a non-zero price associated with that item, and if the amount of credit accumulated is sufficient for purchase of the item selected, to generate a vend signal.

4. Apparatus as set forth in claim 3 further including means for initiating vending of the selected item, said initiating means being respon-sive to the vend signal from the processing means.

5. Apparatus as set forth in claim 4 further including interlocking means for supplying vendor status inputs to the processing means which indicate that the vendor is not ready to vend the desired item.

6. Apparatus as set forth in claim 4 further including a customer inaccessible free vend switch and means for connecting the free vend switch with the processing means, said free vend switch having a first and a second position, the processing means being responsive to said free vend switch being in the first position to generate a vend signal even if the amount of credit accumulated is insufficient for purchase of the item selected.

7. Apparatus as set forth in claim 4 including sensing means for supplying a vendor status input comprising a series of pulses indicating the speed of rotation of a motor in the vendor to the processing means and further including clock means for supplying interrupts to the processing means, said processing means being responsive to the number of pulses supplied by the sensing means during a predetermined number of clock interrupts not falling within a pre-determined range of values to remove the vend signal.

8. Apparatus as set forth in claim 4 wherein the memory has a predetermined address for storing a total ac-cumulated sales figure for the vendor and including means for supplying a control input signal indicating the vending of the selected item to the processing means, said process-ing means being responsive to said signal to update the to-tal sales figure in the memory.

9. Apparatus as set forth in claim 8 including second display means for displaying said total sales figure.

10. Apparatus as set forth in claim 9 wherein the second display means is normally inactivated and further in-cluding means operable by authorized personnel for activat-ing said second display means.

11. Apparatus as set forth in claim 8 including means for supplying a reset control input signal to the pro-cessing means, said processing means being responsive to said reset signal to change the total sales figure stored in memory to zero.

12. Apparatus as set forth in claim 1 including means operable by authorized personnel for setting the val-ues of at least some of the parameters stored in the memory.

13. Apparatus as set forth in claim 12 wherein one of the parameters associated with each item is price, wherein the apparatus has at least two mutually exclusive operation modes, one of said operation modes being a vending mode and one of said operation modes being a price-setting mode, and where-in the parameter value-setting means includes customer in-accessible price-setting means for setting the item prices stored in the memory, further including service-man-operable access means having an open and a closed position for providing a serviceman access to said customer inaccessible price-setting means when said serviceman access means is in its open position and for preventing access to said price-setting means when said serviceman access means is in its closed posi-tion, and mode-setting means for setting the mode of operation of the apparatus, said mode-setting means being operable to set said apparatus in the price-setting mode only when the serviceman access means is open.

14. Apparatus as set forth in claim 13 wherein the customer inaccessible price-setting means includes a price-setting module detachably mounted in a holder, said mode-setting means being responsive to the price-setting module being in its holder to set the apparatus in its vending mode and being responsive to the price-setting module being out of its holder to set the apparatus in its price-setting mode.

15. Apparatus as set forth in claim 13 wherein the mode-setting means includes means for ensuring that the apparatus is set in its vending mode when the access means is closed.

16. Apparatus as set forth in claim 13 wherein the customer inaccessible price-setting means includes an authorized personnel-removable price-setting module and plug means for connecting the price-setting module to the appara-tus, said plug means being authorized personnel accessible by way of the authorized personnel-operable access means and being customer inaccessible.

17. Apparatus as set forth in claim 16 wherein the removable price-setting module is of such a size that an authorized person can hold it in one hand, thereby leaving the authorized person's other hand free to operate said price-setting module.

18. Apparatus as set forth in claim 17 wherein the price-setting module includes the display means.

19. Apparatus as set forth in claim 12 wherein one of the parameters associated with each different item is price, wherein the apparatus has at least two mutually ex-clusive modes of operation, one of said operation modes be-ing a vending mode and one of said operation modes being a price-setting mode, wherein the interrogation means includes a plurality of selection switches corresponding to the items in the vendor, and further including means for setting the mode of operation of the apparatus, the processing means be-ing responsive to the actuation of a selection switch and to the apparatus being in the price setting mode to retrieve from the memory the price of the item corresponding to that selection switch and to supply a coded signal corresponding to said price to the display means, the display means being responsive to the coded price signal from the processing means to display the price of the item corresponding to the actuated selection switch.

20. Apparatus as set forth in claim 19 including means for supplying at least one vendor status input to the processing means representative of a deposit of money in the vendor, said processing means being responsive to the appa-ratus being in the vending mode and to said money deposit input to determine the amount of credit accumulated as a result of said deposit and to supply to said display means a signal corresponding to said accumulated credit, whereby said display means displays said accumulated credit when the apparatus is in the vending mode and displays the price cor-responding to an item whose selection switch is actuated when the apparatus is in the price-setting mode.

21. Apparatus as set forth in claim 19 wherein the serviceman-operable parameter setting means is a price-setting means for setting the prices of the items to be vended, said price setting means including means for supply-ing to the processing means a control input signal repre-senting a potential new price, said processing means being responsive to the apparatus being in the price-setting mode and to said potential new price input signal to supply a coded signal corresponding to said potential new price to the display means, the display means being responsive to the coded potential new price signal to display the potential new price.

22. Apparatus as set forth in claim 21 wherein the price-setting means includes means for putting the appa-ratus in a price loading mode, the processing means being responsive to the apparatus being in the price loading mode and to the actuation of a selection switch to erase the price in the memory address corresponding to the actuated selection switch and to write the potential new price into said corresponding memory address thereby to change the price of the item corresponding to the actuated selection switch from the value stored in the corresponding memory address before the apparatus was put into the price loading mode to the potential new price value, whereby a serviceman can use the price-setting means to cause the display of a potential new price, activate the price loading mode means and actuate a selection switch and thereby change the price of the item selected to the potential new price.

23. Apparatus as set forth in claim 22 wherein the potential new price supplying means includes serviceman-operable dial means for selecting the potential new price, said dial means including a dial having a plurality of pric-es indicated thereon and a control knob having a pointer for indicating a given one of the prices on the dial, whereby a serviceman may select a potential new price by turning the control knob to point to that price on the dial.

24. Apparatus as set forth in claim 22 wherein the potential new price supplying means includes a numeric keyboard having a plurality of keys, the processing means being responsive to the actuation of a key to cause the dis-play means to display the numeral associated with that key.

25. Apparatus as set forth in claim 21 wherein the operation mode setting means incudes means for causing the processing means to cease supplying a coded potential new price signal to the display means upon the apparatus being set from the price setting mode to the vending mode thereby erasing the last price setting appearing in the dis-play means.

26. Apparatus as set forth in claim 19 including incrementing means for supplying a price incrementing con-trol input to the processing means, the processing means be-ing responsive to the price incrementing control input to increment the price shown on the display means.

27. Apparatus as set forth in claim 26 wherein the incrementing means includes means for incrementing the displayed price up and means for incrementing the displayed price down.

28. Apparatus as set forth in claim 26 wherein the incrementing means has at least one state wherein it is activated and at least one state wherein it is deactivated, said processing means being responsive to the incrementing means being in an activated state to continuously increment the displayed price and being responsive to the incrementing means being put in a deactivated state to cease incrementing the displayed price.

29. Apparatus as set forth in claim 28 wherein the incrementing means further includes rapid incrementing enabling means for supplying a control input signal to the processing means to cause the processing means to increment the price displayed by the display means at a rapid rate, the processing means being responsive to the presence of the rapid incrementing control signal to continuously increment the displayed price at a faster rate than in the absence of said signal.

30. Apparatus for controlling the functioning of a vendor for vending a plurality of items, each item having at least one parameter associated therewith, comprising:

a memory having a plurality of addresses for storing values of at least some of the parameters in predetermined memory addresses, the parameter values stored in the predetermined memory addresses being electrically alterable;

processing means responsive to a plurality of vendor status inputs, a plurality of inputs from the memory, and a plural ity of control inputs, for performing arithemetic and logic operations with those inputs and with the values of the par-ameters associated with the items in a sequence controlled by a preselected set of instructions which constitute a pro-gram and for supplying output signals based upon results ob-tained from said operations to control functioning of the vendor, the predetermined memory addresses being accessible by the processing means and the parameter values stored therein being alterable by said processing means;

interrogation means operable by authorized personnel for re-trieving from memory the values of at least some of the par-ameters stored therein;

(Continuing Claim 30) display means for visually displaying to authorized person-nel a parameter value retrieved from memory by the interro-gation means independently of any other input of said proc-essing means being equal in value to the value of the param-eter retrieved from the memory, whereby authorized personnel may utilize the interrogation means to retrieve the value of a desired parameter from the memory;

customer inaccessible means operable by authorized personnel for setting the values of at least some of the parameters stored in the memory, said apparatus having at least two mutually exclusive operation modes, one of said operation modes being a vending mode and one of said operation modes being a parameter-setting mode;

authorized personnel-operable access means having an open and a closed position for providing authorized personnel access to said customer inaccessible parameter-setting means when said access means is in its open position and for pre-venting access to said price-setting means when said access means is in its closed position; and mode-setting means for setting the mode of operation of the apparatus, said mode-setting means being operable to set said apparatus in the price-setting mode only when the ac-cess means is open.

31. Apparatus as set forth in claim 30 wherein the customer inaccessible parameter-setting means incudes a parameter-setting module detachably mounted in a holder, said mode-setting means being responsive to the parameter-setting module being in its holder to set the apparatus in its vending mode and being responsive to the parameter-setting module being out of its holder to set the apparatus in its parameter-setting mode.

32. Apparatus as set forth in claim 30 wherein the mode-setting means includes means for ensuring that the apparatus is set in its vending mode when the access means is closed.

33. Apparatus as set forth in claim 30 wherein the customer inaccessible price-setting means includes an authorized personnel-removable parameter-setting module and plug means for connecting the price-setting module to the apparatus, said plug means being authorized personnel acces-sible by way of the access means and being customer inacces-sible.

34. Apparatus as set forth in claim 30 wherein the parameter-setting means includes means for putting the apparatus in a parameter-loading mode, and means for select-ing an item having a parameter which is to be changed, the processing means being responsive to the apparatus being in the parameter-loading mode and to the selecting means to (continuing claim 34) erase a prameter value in the memory address corresponding to the selected item and to write a new parameter value into said corresponding memory address thereby to change a param-eter of the item from the value stored in the corresponding memory address before the apparatus was put into the parameter-loading mode to a new parameter value, whereby authorized personnel can use the parameter-setting means to change the value of a parameter of a selected item to a new parameter value.

35. Apparatus as set forth in claim 1 including incrementing means for supplying a parameter incrementing control input to the processing means, the processing means being responsive to the parameter incrementing control input to increment the parameter shown on the display means.

36. Apparatus as set forth in claim 35 wherein the incrementing means includes means for incrementing the displayed parameter up and means for incrementing the dis-played parameter down.

37. Apparatus as set forth in claim 35 wherein the incrementing means has at least one state wherein it is activated and at least one state wherein it is deactivated, said processing means being responsive to the incrementing means being in an activated state to continuously increment (Continuing Claim 37) the displayed parameter and being responsive to the incre-menting means being put in a deactivated state to cease in-crementing the displayed parameter.

38. Apparatus as set forth in claim 37 wherein the incrementing means further includes rapid incrementing enabling means for supplying a control input signal to the processing means to cause the processing means to increment the parameter displayed by the display means at a rapid rate, the processing means being responsive to the presence of the rapid incrementing control signal to continuously in-crement the displayed prameter at a faster rate than in the absence of said signal.